Abstract: A method and apparatus are disclosed from the perspective of a network. In one embodiment, the method includes the network transmitting a Semi-Persistent Scheduling (SPS) configuration to a User Equipment (UE) for configuring a second Physical Downlink Shared Channel (PDSCH). The method also includes the network transmitting a configuration to the UE for configuring a first monitoring occasion for a first Physical Downlink Control Channel (PDCCH) and a second monitoring occasion for a second PDCCH, wherein the second PDCCH is associated with the first PDCCH. The method further includes the network not allowing the first PDCCH and the second PDCCH to schedule the UE with a first PDSCH partially or fully overlapping with the second PDSCH in time domain, wherein a last symbol of a later monitoring occasion among the first and the second monitoring occasion ends less than a processing threshold before a starting symbol of the second PDSCH.

Abstract: A switch device includes a P-type substrate, a first gate structure, a first N-well, a shallow trench isolation structure, a first P-well, a second gate structure, a first N-type doped region, a second P-well, and a second N-type doped region. The first N-well is formed in the P-type substrate and partly under the first gate structure. The shallow trench isolation structure is formed in the first N-well and under the first gate structure. The first P-well is formed in the P-type substrate and under the first gate structure. The first N-type doped region is formed in the P-type substrate and between the first gate structure and the second gate structure. The second P-well is formed in the P-type substrate and under the second gate structure. The second N-type doped region is formed in the second P-well and partly under the second gate structure.

Abstract: A memory cell array of a multi-time programmable non-volatile memory includes plural memory cells. The memory cell has the structure of 1T1C cell, 2T1C cell or 3T1C cell. Moreover, the floating gate transistors of the memory cells in different rows of the memory cell array are constructed in the same well region. Consequently, the chip size is reduced. Moreover, by providing proper bias voltages to the memory cell array, the program action, the erase action or the read action can be performed normally.

Abstract: A color filter array includes a first color resist, a second color resist, and a third color resist. The first color resist has a first color, the second color resist has a second color, and the third color resist has a third color. A transparency of the third color resist is greater than transparencies of the first color resist and the second color resist. The first color resist has a first edge and a second edge arranged along a first direction. The second color resist has a first edge and a second edge arranged along a first direction. The first color resist and the second color resist are arranged along a second direction. The first edge of the first color resist, the second edge of the second color resist, and the second edge of the first color resist are arranged sequentially along the first direction.

Abstract: A switch device includes a P-type substrate, a first gate structure, a first N-well, a shallow trench isolation structure, a first P-well, a second gate structure, a first N-type doped region, a second P-well, and a second N-type doped region. The first N-well is formed in the P-type substrate and partly under the first gate structure. The shallow trench isolation structure is formed in the first N-well and under the first gate structure. The first P-well is formed in the P-type substrate and under the first gate structure. The first N-type doped region is formed in the P-type substrate and between the first gate structure and the second gate structure. The second P-well is formed in the P-type substrate and under the second gate structure. The second N-type doped region is formed in the second P-well and partly under the second gate structure.

Abstract: An antenna structure includes a first radiation element, a second radiation element, a third radiation element, a fourth radiation element, a fifth radiation element, and a dielectric substrate. The first radiation element has a positive feeding point. The second radiation element is coupled to the first radiation element. The third radiation element has a negative feeding point. The fourth radiation element is coupled to the third radiation element. The fifth radiation element is floating. The dielectric substrate has a first surface and a second surface which are opposite to each other. The first radiation element and the third radiation element are both disposed on the first surface of the dielectric substrate. The second radiation element, the fourth radiation element, and the fifth radiation element are all disposed on the second surface of the dielectric substrate.

Abstract: A semiconductor package includes a first chip and a second chip arranged side by side on a carrier substrate. The first chip is provided with a high-speed signal pads along a first side in proximity to the second chip. The second chip includes a redistribution layer, and the redistribution layer is provided with data (DQ) pads along the second side in proximity to the first chip. A plurality of first bonding wires is provided to directly connect the high-speed signal pads to the DQ pads. The redistribution layer of the second chip is provided with first command/address (CA) pads along the third side opposite to the second side, and a plurality of dummy pads corresponding to the first CA pads. The plurality of dummy pads are connected to second CA pads disposed along a fourth side of the second chip via interconnects of the redistribution layer.

Abstract: An antenna structure includes a first radiation element, a second radiation element, a third radiation element, a fourth radiation element, a fifth radiation element, and a dielectric substrate. The first radiation element has a positive feeding point. The second radiation element is coupled to the first radiation element. The third radiation element has a negative feeding point. The fourth radiation element is coupled to the third radiation element. The fifth radiation element is floating. The dielectric substrate has a first surface and a second surface which are opposite to each other. The first radiation element and the third radiation element are both disposed on the first surface of the dielectric substrate. The second radiation element, the fourth radiation element, and the fifth radiation element are all disposed on the second surface of the dielectric substrate.

Abstract: An electrophoretic display device includes an electrophoretic display module, and a polymer light emitting diode (PLED) module. The polymer light emitting diode (PLED) module is over the electrophoretic display module, and is aligned with and is attached to the electrophoretic display module. In a dark environment, the polymer light emitting diode (PLED) module can emit light to supplement the insufficient ambient light, so that the users may observe the information or pattern displayed by the electrophoretic display device. The electrophoretic display device can be a flexible electrophoretic display device.

Abstract: A front plate laminate structure includes a display medium layer, a top adhesive layer, a transparent substrate, a transparent conductive film, and a color filter layer. The top adhesive layer is located on the display medium layer. The transparent substrate is located on the top adhesive layer. The transparent conductive film is located between the transparent substrate and the top adhesive layer. The transparent conductive film includes a bottom surface facing the top adhesive layer. The color filter layer is located between the transparent substrate and the display medium layer.

Abstract: A package structure and a method of forming the same are provided. A method includes forming first electrical connectors and second electrical connectors on a first side of an interposer wafer. An integrated circuit die is bonded to the first side of the interposer wafer using the first electrical connectors. A stiffener structure is attached to the first side of the interposer wafer adjacent the integrated circuit die. The stiffener structure covers the second electrical connectors in a plan view. The integrated circuit die and the stiffener structure are encapsulated with a first encapsulant. The interposer wafer and the stiffener structure are singulated to form a stacked structure.

Abstract: An electronic package structure and a chip thereof are provided. The electronic package structure includes a substrate, a chip, a plurality of signal wires, and a core ground wire. The chip disposed on and electrically connected to the substrate has a core wiring region and an input and output pad region located at a top surface thereof. The input and output pad region is located between the core wiring region and an edge of the chip. The chip includes a plurality of signal pads in the input and output region and a core ground pad adjacent to one of the signal pads. The core ground pad located in the core wiring region. The signal wires are respectively connected to the signal pads. The core ground wire connected to the core ground pad is adjacent to and shields one of the signal wires.

Abstract: A color filter array for a reflective display device includes a plurality of first filter arrays, a plurality of second filter arrays, and a plurality of third filter arrays. Each of the first filter arrays has a plurality of first filter patterns separated from each other. Each of the second filter arrays has a plurality of second filter patterns separated from each other. Each of the third filter arrays has a plurality of third filter patterns separated from each other. Each of the first filter arrays is adjacent to one of the second filter arrays and one of the third filter arrays.

Abstract: A semiconductor package includes a carrier substrate including opposite first surface and second surface; a first chip and a second chip mounted on the first surface of the carrier substrate in a side-by-side manner, wherein the first chip has a plurality of high-speed signal pads disposed along its first side adjacent to the second chip, and the second chip has a plurality of data (DQ) pads along its second side adjacent to the first chip; and a plurality of first bonding wires, directly connecting the plurality of high-speed signal pads to the plurality of data (DQ) pads.

Abstract: A fastening device includes a fixing nut and a fixing base. The fixing base includes a base plate, an anti-falling wall, a door piece, and an anti-tilt arm. The anti-falling wall, the door piece and the anti-tilt arm are formed on the base plate, and the anti-tilt arm is arranged opposite to the door piece. An accommodation space is formed between the anti-falling wall, the door piece and the anti-tilt arm, and the fixing nut is rotatably arranged in the accommodation space. In addition, a heat dissipation module with the fastening device is also disclosed herein.

Abstract: A heat dissipation base includes a fixing plate and a metal heat conduction block. The fixing plate includes a plurality of heat pipe partitions and a plurality of heat pipe fixing openings, and the heat pipe fixing openings are formed between the heat pipe partitions. The metal heat conduction block is fixed to the fixing plate, and the fixing plate further includes a plurality of supporting portions to support shear surfaces at two ends of the heat conduction block.

Abstract: A multi-time programming non-volatile memory includes a select transistor, a floating gate transistor, a switch transistor, a capacitor and an erase gate element. The select transistor is connected with a select line and a source line. The floating gate transistor includes a floating gate. The floating gate transistor is connected with the select transistor. The switch transistor is connected with a word line, the floating gate transistor and a bit line. A first terminal of the capacitor is connected with the floating gate. A second terminal of the capacitor is connected with a control line. The erase gate element includes the floating gate, a gate oxide layer and a p-type region. The erase gate element is connected with an erase line. The floating gate of the erase gate element at least includes an n-type floating gate part.

Abstract: In an embodiment, a device includes: a first redistribution structure including a first dielectric layer; a die adhered to a first side of the first redistribution structure; an encapsulant laterally encapsulating the die, the encapsulant being bonded to the first dielectric layer with first covalent bonds; a through via extending through the encapsulant; and first conductive connectors electrically connected to a second side of the first redistribution structure, a subset of the first conductive connectors overlapping an interface of the encapsulant and the die.

Abstract: A semiconductor package includes a first chip and a second chip arranged side by side on a carrier substrate. The first chip is provided with a high-speed signal pads along a first side in proximity to the second chip. The second chip includes a redistribution layer, and the redistribution layer is provided with data (DQ) pads along the second side in proximity to the first chip. A plurality of first bonding wires is provided to directly connect the high-speed signal pads to the DQ pads. The redistribution layer of the second chip is provided with first command/address (CA) pads along the third side opposite to the second side, and a plurality of dummy pads corresponding to the first CA pads. The plurality of dummy pads are connected to second CA pads disposed along a fourth side of the second chip via interconnects of the redistribution layer.

Abstract: A memory cell array of a multi-time programmable non-volatile memory includes plural memory cells. The memory cell has the structure of 1T1C cell, 2T1C cell or 3T1C cell. Moreover, the floating gate transistors of the memory cells in different rows of the memory cell array are constructed in the same well region. Consequently, the chip size is reduced. Moreover, by providing proper bias voltages to the memory cell array, the program action, the erase action or the read action can be performed normally.