Abstract: The color electrophoretic display includes a display region, a pixel array, a display medium layer, and a color filter array. The display region includes multiple sub-pixel regions. The pixel array corresponds to the display region in position. The display medium layer is located on the pixel array. The color filter array is located on the display medium layer. The color filter array includes multiple color resists. A portion of the color resists include a first pixel fill factor, another portion of the color resists include a second pixel fill factor, the second pixel fill factor is smaller than the first pixel fill factor, and the first pixel fill factor and the second pixel fill factor are smaller than 60%.

Abstract: A color filter array includes a first color resist having a first color, a second color resist having a second color different from the first color, and a third color resist having a second color different from the first color and the second color. The first color resist includes multiple sections. The second color resist includes multiple sections. The third color resist includes multiple sections. When viewed in a plan view, the sections of the first color resist collectively arranged as a continuous S shape, the sections of the second color resist collectively arranged as a continuous S shape, and the sections of the third color resist collectively arranged as a continuous S shape.

Abstract: An electronic device is provided, including a housing, a first slot, a second slot, and a circuit board. The first and second slots are formed on the housing and spaced apart from each other. The circuit board is disposed in the housing and includes a first antenna structure and a second antenna structure. The first antenna structure has a Z-shaped conductive body, and the second antenna structure includes a microstrip portion and a base portion. The base portion is electrically connected to the conductive body, and the microstrip portion is spaced apart from the base portion.

Abstract: A chip package structure includes an interposer structure that contains a package-side redistribution structure, an interposer core assembly, and a die-side redistribution structure. The interposer core assembly includes at least one silicon substrate interposer, and each of the at least one silicon substrate interposer includes a respective silicon substrate, a respective set of through-silicon via (TSV) structures vertically extending through the respective silicon substrate, a respective set of interconnect-level dielectric layers embedding a respective set of metal interconnect structures, and a respective set of metal bonding structures that are electrically connected to the die-side redistribution structure. The chip package structure includes at least two semiconductor dies that are attached to the die-side redistribution structure, and an epoxy molding compound (EMC) multi-die frame that laterally encloses the at least two semiconductor dies.

Abstract: In an embodiment, a device includes: a first redistribution structure including a first dielectric layer; a die adhered to a first side of the first redistribution structure; an encapsulant laterally encapsulating the die, the encapsulant being bonded to the first dielectric layer with first covalent bonds; a through via extending through the encapsulant; and first conductive connectors electrically connected to a second side of the first redistribution structure, a subset of the first conductive connectors overlapping an interface of the encapsulant and the die.

Abstract: An electronic device is provided, including a housing, a first slot, a second slot, and a circuit board. The first and second slots are formed on the housing and spaced apart from each other. The circuit board is disposed in the housing and includes a first antenna structure and a second antenna structure. The first antenna structure has a Z-shaped conductive body, and the second antenna structure includes a microstrip portion and a base portion. The base portion is electrically connected to the conductive body, and the microstrip portion is spaced apart from the base portion.

Abstract: A semiconductor package includes a semiconductor device, an encapsulating material, a redistribution structure, and an adhesive residue. The encapsulating material encapsulates a first part of a side surface of the semiconductor device. The redistribution structure is disposed over the semiconductor device and a first side of the encapsulating material. The adhesive residue is disposed over a second side of the encapsulating material opposite to the first side and surrounding the semiconductor device, wherein the adhesive residue encapsulates a second part of the side surface of the semiconductor device.

Abstract: A random code generating method for the magnetoresistive random access memory is provided. Firstly, a first magnetoresistive random access memory cell and a second magnetoresistive random access memory cell are programmed into an anti-parallel state. Then, an initial value of a control current is set. Then, an enroll action is performed on the first and second magnetoresistive random access memory cells. If the first and second magnetoresistive random access memory cells fail to pass the verification action, the control current is increased by a current increment, and the step of setting the control current is performed again. If the first and second magnetoresistive random access memory cells pass the verification action, a one-bit random code is stored in the first magnetoresistive random access memory cell or the second magnetoresistive random access memory cell.

Abstract: A front plate laminate structure includes a display medium layer, a top adhesive layer, a transparent substrate, a transparent conductive film, and a color filter layer. The top adhesive layer is located on the display medium layer. The transparent substrate is located on the top adhesive layer. The transparent conductive film is located between the transparent substrate and the top adhesive layer. The transparent conductive film includes a bottom surface facing the top adhesive layer. The color filter layer is located between the transparent substrate and the display medium layer.

Abstract: A heat dissipation base includes a fixing plate and a metal heat conduction block. The fixing plate includes a plurality of heat pipe partitions and a plurality of heat pipe fixing openings, and the heat pipe fixing openings are formed between the heat pipe partitions. The metal heat conduction block is fixed to the fixing plate, and the fixing plate further includes a plurality of supporting portions to support shear surfaces at two ends of the heat conduction block.

Abstract: A circuit board and an electronic apparatus using the same are provided. The circuit board includes an integrated-circuit (IC) device arrangement region and an electronic device arrangement region. The circuit board includes a first external wiring layer and an inner wiring layer. The first external wiring layer includes a plurality of first signal traces and a ground extending portion that extend from the IC device arrangement region to the electronic device arrangement region. The inner wiring layer includes a ground portion and an inner signal trace. The ground portion defines an opening region, and the inner signal trace is located in the opening region and extends from a position under the IC device arrangement region to another position under the electronic device region. The ground extending portion and the opening region overlap with each other in a thickness direction of the circuit board.

Abstract: In an embodiment, a device includes: a first redistribution structure including a first dielectric layer; a die adhered to a first side of the first redistribution structure; an encapsulant laterally encapsulating the die, the encapsulant being bonded to the first dielectric layer with first covalent bonds; a through via extending through the encapsulant; and first conductive connectors electrically connected to a second side of the first redistribution structure, a subset of the first conductive connectors overlapping an interface of the encapsulant and the die.

Abstract: A manufacturing method of a semiconductor package includes at least the following steps. A rear surface of a semiconductor die is attached to a patterned dielectric layer of a first redistribution structure through a die attach material, where a thickness of a portion of the die attach material filling a gap between the rear surface of the semiconductor die and a recessed area of the patterned dielectric layer is greater than a thickness of another portion of the die attach material interposed between the rear surface of the semiconductor die and a non-recessed area of the patterned dielectric layer. An insulating encapsulant is formed on the patterned dielectric layer of the first redistribution structure to cover the semiconductor die and the die attach material. Other methods for forming a semiconductor package are also provided.

Abstract: A package structure and a method of forming the same are provided. A method includes forming first electrical connectors and second electrical connectors on a first side of an interposer wafer. An integrated circuit die is bonded to the first side of the interposer wafer using the first electrical connectors. A stiffener structure is attached to the first side of the interposer wafer adjacent the integrated circuit die. The stiffener structure covers the second electrical connectors in a plan view. The integrated circuit die and the stiffener structure are encapsulated with a first encapsulant. The interposer wafer and the stiffener structure are singulated to form a stacked structure.

Abstract: An electrophoretic display device, including an electrophoretic display panel and a display driving module, is provided. The display driving module is coupled to the electrophoretic display panel and is used for driving the electrophoretic display panel. The display driving module generates multiple first grayscale images according to multiple color pixel values of multiple color pixels corresponding to multiple colors of a color image. The display driving module captures multiple grayscale values of multiple locations of multiple first sub-pixels of the first grayscale images according to multiple locations of multiple mask sub-pixels corresponding to the colors in a mask image to generate multiple second grayscale images. The display driving module synthesizes the second grayscale images to generate a synthesized image. The display driving module drives the electrophoretic display panel according to the synthesized image.

Abstract: A color filter module is provided. The color filter module is arranged on a display panel. The color filter module includes a transparent substrate and a color resist layer. The transparent substrate includes multiple sub-pixel regions arranged in an array. The color resist layer is arranged on the transparent substrate. The color resist layer includes multiple color resist units. The color resist units are respectively arranged across at least two sub-pixel regions, and the color resist units form a staggered array on the transparent substrate.

Abstract: A circuit board and an electronic apparatus using the same are provided. The circuit board includes an integrated-circuit (IC) device arrangement region and an electronic device arrangement region. The circuit board includes a first external wiring layer and an inner wiring layer. The first external wiring layer includes a plurality of first signal traces and a ground extending portion that extend from the IC device arrangement region to the electronic device arrangement region. The inner wiring layer includes a ground portion and an inner signal trace. The ground portion defines an opening region, and the inner signal trace is located in the opening region and extends from a position under the IC device arrangement region to another position under the electronic device region. The ground extending portion and the opening region overlap with each other in a thickness direction of the circuit board.

Abstract: A chip package structure includes an interposer structure that contains a package-side redistribution structure, an interposer core assembly, and a die-side redistribution structure. The interposer core assembly includes at least one silicon substrate interposer, and each of the at least one silicon substrate interposer includes a respective silicon substrate, a respective set of through-silicon via (TSV) structures vertically extending through the respective silicon substrate, a respective set of interconnect-level dielectric layers embedding a respective set of metal interconnect structures, and a respective set of metal bonding structures that are electrically connected to the die-side redistribution structure. The chip package structure includes at least two semiconductor dies that are attached to the die-side redistribution structure, and an epoxy molding compound (EMC) multi-die frame that laterally encloses the at least two semiconductor dies.

Abstract: A color filter module is provided. The color filter module is disposed on an electrophoretic display panel. The color filter module includes a transparent substrate and a color resist layer. The transparent substrate includes a plurality of pixel regions arranged in an array. Each of the plurality of pixel regions includes a plurality of sub-pixel regions. The color resist layer is disposed on the transparent substrate. Among the plurality of sub-pixel regions of the transparent substrate, a first sub-pixel region and a second sub-pixel region that correspond to a same color and are adjacent to each other are provided with a plurality of color resist units of the same color of the color resist layer. The plurality of color resist units are arranged in an array and arranged in a discontinuous pattern.

Abstract: A package structure and a method of forming the same are provided. A method includes forming first electrical connectors and second electrical connectors on a first side of an interposer wafer. An integrated circuit die is bonded to the first side of the interposer wafer using the first electrical connectors. A stiffener structure is attached to the first side of the interposer wafer adjacent the integrated circuit die. The stiffener structure covers the second electrical connectors in a plan view. The integrated circuit die and the stiffener structure are encapsulated with a first encapsulant. The interposer wafer and the stiffener structure are singulated to form a stacked structure.