Abstract: A chip package structure includes an interposer structure that contains a package-side redistribution structure, an interposer core assembly, and a die-side redistribution structure. The interposer core assembly includes at least one silicon substrate interposer, and each of the at least one silicon substrate interposer includes a respective silicon substrate, a respective set of through-silicon via (TSV) structures vertically extending through the respective silicon substrate, a respective set of interconnect-level dielectric layers embedding a respective set of metal interconnect structures, and a respective set of metal bonding structures that are electrically connected to the die-side redistribution structure. The chip package structure includes at least two semiconductor dies that are attached to the die-side redistribution structure, and an epoxy molding compound (EMC) multi-die frame that laterally encloses the at least two semiconductor dies.

Abstract: An antenna system includes a first antenna element and a second antenna element. The first antenna element includes a first ground element, a first radiation element, a second radiation element, and a third radiation element. The first radiation element has a first feeding point. The second radiation element is coupled to the first ground element. The third radiation element is coupled to the first ground element. The third radiation element is adjacent to the first radiation element and the second radiation element. The second antenna element includes a second ground element, a fourth radiation element, a fifth radiation element, and a sixth radiation element. The fourth radiation element has a second feeding point. The fifth radiation element is adjacent to the fourth radiation element. The fifth radiation element is coupled through the sixth radiation element to the second ground element.

Abstract: In an embodiment, a device includes: a first redistribution structure including a first dielectric layer; a die adhered to a first side of the first redistribution structure; an encapsulant laterally encapsulating the die, the encapsulant being bonded to the first dielectric layer with first covalent bonds; a through via extending through the encapsulant; and first conductive connectors electrically connected to a second side of the first redistribution structure, a subset of the first conductive connectors overlapping an interface of the encapsulant and the die.

Abstract: A package structure and a method of forming the same are provided. A method includes forming first electrical connectors and second electrical connectors on a first side of an interposer wafer. An integrated circuit die is bonded to the first side of the interposer wafer using the first electrical connectors. A stiffener structure is attached to the first side of the interposer wafer adjacent the integrated circuit die. The stiffener structure covers the second electrical connectors in a plan view. The integrated circuit die and the stiffener structure are encapsulated with a first encapsulant. The interposer wafer and the stiffener structure are singulated to form a stacked structure.

Abstract: A random code generating method for the magnetoresistive random access memory is provided. Firstly, a first magnetoresistive random access memory cell and a second magnetoresistive random access memory cell are programmed into an anti-parallel state. Then, an initial value of a control current is set. Then, an enroll action is performed on the first and second magnetoresistive random access memory cells. If the first and second magnetoresistive random access memory cells fail to pass the verification action, the control current is increased by a current increment, and the step of setting the control current is performed again. If the first and second magnetoresistive random access memory cells pass the verification action, a one-bit random code is stored in the first magnetoresistive random access memory cell or the second magnetoresistive random access memory cell.

Abstract: A display device includes a panel, a conductive layer, a first color filter array and a second color filter array. The panel has a display surface and multiple sub-pixel regions where the multiple sub-pixel regions and the conductive layer are on this display surface. The first color filter array including multiple first color filter elements is disposed on the conductive layer while the second color filter array including multiple second color filter elements is disposed on the first color filter array. One first overlaid region and one second overlaid region are defined by the orthogonal projections of the color filter elements within one of the sub-pixel regions. In one sub-pixel region, a section of the first overlaid region does not overlap a section of the second overlaid region.

Abstract: A software developer proxy tool accesses microservice applications for a software development project by connecting the developer proxy tool to a common port on a computer network. The tool implements software and hardware to register a plurality of the microservice applications on connection ports that connect to the developer proxy tool at an address for the common port. Data requests among the microservices are handled by the developer proxy tool via the common port. The tool sequentially queries selected microservice applications on the respective connection ports to determine availability for completing a request. The tool receives responses back from microservices and directs the responses back to the requesting program. Failed requests trigger use of remote or third party microservice applications that may be available over an internet connection.

Abstract: A power diode device includes a substrate. The substrate includes a core layer of a first conductive type, a first diffusion layer of the first conductive type, a second diffusion layer of a second conductive type, and a heavily doped region of the second conductive type. The core layer is located between the first diffusion layer and the second diffusion layer. A thickness of the core layer is greater than that of the second diffusion layer. The heavily doped region is located in the second diffusion layer and extends toward the core layer to form a PN junction between the heavily doped region and the core layer. A method for manufacturing the power diode device is also provided.

Abstract: A reflective display with a color compensation layer includes a driving substrate, a display medium layer located on the driving substrate, a color filter array, an adhesive layer located on the display medium layer, and a color compensation layer. The driving substrate includes a first sub-pixel region, a second sub-pixel region, and a third sub-pixel region. The color filter array includes a red color resist, a green color resist, and a blue color resist. The color filter array and the color compensation layer are located at opposite two sides of the adhesive layer. The color compensation layer includes a first blue ink layer. A vertical projection of the green color resist on the driving substrate overlaps the second sub-pixel region. A vertical projection of the first blue ink layer on the driving substrate at least partially overlaps the second sub-pixel region.

Abstract: An antenna system includes a first antenna element and a second antenna element. The first antenna element includes a first ground element, a first radiation element, a second radiation element, and a third radiation element. The first radiation element has a first feeding point. The second radiation element is coupled to the first ground element. The third radiation element is coupled to the first ground element. The third radiation element is adjacent to the first radiation element and the second radiation element. The second antenna element includes a second ground element, a fourth radiation element, a fifth radiation element, and a sixth radiation element. The fourth radiation element has a second feeding point. The fifth radiation element is adjacent to the fourth radiation element. The fifth radiation element is coupled through the sixth radiation element to the second ground element.

Abstract: A switch device includes a P-type substrate, a first gate structure, a first N-well, a shallow trench isolation structure, a first P-well, a second gate structure, a first N-type doped region, a second P-well, and a second N-type doped region. The first N-well is formed in the P-type substrate and partly under the first gate structure. The shallow trench isolation structure is formed in the first N-well and under the first gate structure. The first P-well is formed in the P-type substrate and under the first gate structure. The first N-type doped region is formed in the P-type substrate and between the first gate structure and the second gate structure. The second P-well is formed in the P-type substrate and under the second gate structure. The second N-type doped region is formed in the second P-well and partly under the second gate structure.

Abstract: A programming method of a non-volatile memory cell is provided. The non-volatile memory cell includes a memory transistor. Firstly, a current limiter is provided, and the current limiter is connected between a drain terminal of the memory transistor and a ground terminal. Then, a program voltage is provided to a source terminal of the memory transistor, and a control signal is provided to a gate terminal of the memory transistor. In a first time period of a program action, the control signal is gradually decreased from a first voltage value, so that the memory transistor is firstly turned off and then slightly turned on. When the memory transistor is turned on, plural hot electrons are injected into a charge trapping layer of the memory transistor.

Abstract: A level shifter includes a cross-coupled transistor pair, first through third cascode transistor pairs and a differential input pair sequentially coupled in series, and further includes a sub level shifter. The first cascode transistor pair is controlled by a first reference voltage. The second cascode transistor pair is controlled by a pair of differential control voltages. The third cascode transistor pair is controlled by a second reference voltage lower than the first reference voltage. The differential input pair is controlled by a pair of differential input voltages. The sub level shifter generates the differential control voltages according to the differential input voltages and the first and second reference voltages. The differential control voltages are switched between the first and second reference voltages. The level shifter outputs a pair of differential output voltages through inverted and non-inverted output terminals coupled with the second cascode transistor pair.

Abstract: An embodiment semiconductor device may include an electrical interconnect layer, a bonding pad electrically coupled to the electrical interconnect layer, a stacked film structure including a first film partially covering a surface of the bonding pad and a second film partially covering the first film, a first aperture formed in the first film over a portion of the surface of the bonding pad, a second aperture formed in the second film such that the second aperture is larger than the first aperture and is formed over the first aperture such that the first aperture is located entirely below an area of the second aperture, and a solder material portion formed in contact with the bonding pad. The solder material portion may include a first width that is less than a size of the second aperture such that the solder material portion does not contact the second film.

Abstract: A ball grid array and a configuration method of the same are provided. The ball grid array is formed on a printed circuit board and includes an inner row region and an outer row region. The inner row region includes a plurality of first solder balls that are arranged by a first ball pitch. The first solder balls respectively correspond to a plurality of predetermined vias, and the first ball pitch is determined according to a minimum trace width that is relative to a via size of the predetermined vias. The outer row region surrounds the inner row region and includes a plurality of second solder balls that are arranged by a second ball pitch. The second ball pitch is smaller than the first ball pitch.

Abstract: A color filter array includes a first color resist, a second color resist, and a third color resist. The first color resist has a first color, the second color resist has a second color, and the third color resist has a third color. A transparency of the third color resist is greater than transparencies of the first color resist and the second color resist. The first color resist has a first edge and a second edge arranged along a first direction. The second color resist has a first edge and a second edge arranged along a first direction. The first color resist and the second color resist are arranged along a second direction. The first edge of the first color resist, the second edge of the second color resist, and the second edge of the first color resist are arranged sequentially along the first direction.

Abstract: A reflective display device includes an electrophoretic display (EPD) module, an optical layer, a color filter layer, and at least one quantum dot (QD). The optical layer is located above the electrophoretic display module. The color filter layer is located on the optical layer. The quantum dot is located between the optical layer and the electrophoretic display module. When first light passes through the optical layer and transmits to the quantum dot, the quantum dot emits second light, and the electrophoretic display module is configured to reflect the second light to irradiate outwards from the color filter layer.

Abstract: A color electrophoretic display includes a display region, a pixel array, a display medium layer, an optical layer, a first color filter array, and a second color filter array. The display region includes multiple sub-pixel regions. The pixel array corresponds to the display region in position. The display medium layer is located on the pixel array. The optical layer is located on the display medium layer. The first color filter array is located on the optical layer. The second color filter array is located between the display medium layer and the optical layer.

Abstract: This disclosure is directed to an X-ray security device having a main body, a conveyor, and a lead curtain. The main body has an opening. The conveyor passes through the opening and is disposed on a bottom of the opening. The lead curtain is hung on the main body and covers the opening, the lead curtain has a pair of outer modules and a central module, the pair of outer modules are arranged corresponding to two sides of a transport direction of the conveyor, and the central module is disposed between the outer modules. A lead equivalent thickness of each outer module is larger than a lead equivalent thickness of the central module, and a weight of the central module is less than a weight of each outer module.

Abstract: This disclosure is directed to an X-ray security device having a main body, a conveyor, and a lead curtain. The main body has an opening. The conveyor passes through the opening and is disposed on a bottom of the opening. The lead curtain is hung on the main body and covers the opening, the lead curtain has a pair of outer modules and a central module, the pair of outer modules are arranged corresponding to two sides of a transport direction of the conveyor, and the central module is disposed between the outer modules. A lead equivalent thickness of each outer module is larger than a lead equivalent thickness of the central module, and a weight of the central module is less than a weight of each outer module.