Patents by Inventor Yuan Lu

Yuan Lu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11489078
    Abstract: A semiconductor structure and a method of forming the same are provided. A semiconductor structure according to the present disclosure includes a first channel member and a second channel member disposed over the first channel member, a first channel extension feature coupled to the first channel member, a second channel extension feature coupled to the second channel member, and an inner spacer feature disposed between the first channel extension feature and the second channel extension feature.
    Type: Grant
    Filed: October 27, 2020
    Date of Patent: November 1, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Wei-Jen Lai, Wei-Yuan Lu, Chih-Hao Yu, Chia-Pin Lin
  • Publication number: 20220336307
    Abstract: A package includes a device die, an encapsulant encapsulating the device die therein, a first plurality of through-vias penetrating through the encapsulant, a second plurality of through-vias penetrating through the encapsulant, and redistribution lines over and electrically coupling to the first plurality of through-vias. The first plurality of through-vias include an array. The second plurality of through-vias are outside of the first array, and the second plurality of through-vias are larger than the first plurality of through-vias.
    Type: Application
    Filed: June 30, 2022
    Publication date: October 20, 2022
    Inventors: Hung-Jui Kuo, Tai-Min Chang, Hui-Jung Tsai, De-Yuan Lu, Ming-Tan Lee
  • Publication number: 20220317336
    Abstract: The present invention discloses a dyeable 1.74 resin lens and a preparation method thereof. The resin lens includes a module layer with a refractive index being 1.74, a dyeable layer with a refractive index being 1.60 is poured on an upper surface of the module layer, an upward curved degree of the dyeable layer is the same as an upward curved degree of the module layer, and a center thickness of the dyeable layer is 0.5-1.2 mm. According to the dyeable 1.74 resin lens of the present invention, a layer of dyeable 1.60plus resin lens is attached to a surface of a 1.74 lens, dyeing performance is good, a visible light transmittance can reach 10-30%, and the blank that the 1.74 lens cannot be dyed is filled.
    Type: Application
    Filed: May 31, 2021
    Publication date: October 6, 2022
    Inventors: Chuanbao WANG, Xinbiao LIU, Qiu DU, Yulei BAO, Yuan LU, Qingbo YAN, Jian HUANG
  • Publication number: 20220302299
    Abstract: The present application provides a semiconductor device and the method of making the same. The method includes recessing a fin extending from a substrate, forming a base epitaxial feature on the recessed fin, forming a bar-like epitaxial feature on the base epitaxial feature, and forming a conformal epitaxial feature on the bar-like epitaxial feature. The forming of the bar-like epitaxial feature includes in-situ doping the bar-like epitaxial feature with an n-type dopant at a first doping concentration. The forming of the conformal epitaxial feature includes in-situ doping the conformal epitaxial feature with a second doping concentration greater than the first doping concentration.
    Type: Application
    Filed: June 6, 2022
    Publication date: September 22, 2022
    Inventors: Chun-An Lin, Wei-Yuan Lu, Feng-Cheng Yang, Tzu-Ching Lin, Li-Li Su
  • Patent number: 11434392
    Abstract: The present teachings contemplate a method comprising providing a first and second substrate, locating an initiator onto a surface of the first or second substrate, the initiator including a substance for initiating polymerization of a polymerizable adhesive, locating the polymerizable adhesive onto a surface of the first and second substrate, the adhesive including a monofunctional, difunctional, or multifunctional methylene malonate, or cyanoacrylate, and contacting first and second substrate.
    Type: Grant
    Filed: September 19, 2017
    Date of Patent: September 6, 2022
    Assignee: Zephyros, Inc.
    Inventors: Michael Czaplicki, Ken Mazich, Yuan Lu, Kevin Hicks, Austin O'Connor, Jason Walker
  • Publication number: 20220251542
    Abstract: An AAV library, comprising AAV variants having an amino acid sequence corresponding to the position amino acids 585 to 597 or 598 of AAV8 or the position amino acids 583 to 595 or 596 of AAV9, and the polynucleotide, host cells, thereof. A method of generating and screening an AAV library and its use.
    Type: Application
    Filed: October 15, 2020
    Publication date: August 11, 2022
    Inventors: Qunsheng JI, Yuan LU, Qing LIN, Yixiong CHEN
  • Patent number: 11403534
    Abstract: The present disclosure discloses a chatbot with a stance taking. Opinions may be extracted from candidate replies during a processing of conversation, and the extracted opinions may be compared with the stance taken by the chatbot so as to perform selection on the candidate replies and remove the candidate replies which have conflicts with the stance taken by the chatbot. With such technical solutions, the stance taken by the chatbot may be exhibited.
    Type: Grant
    Filed: May 13, 2019
    Date of Patent: August 2, 2022
    Assignee: Microsoft Technology Licensing, LLC
    Inventors: Bai Su, Chao Ma, Changhai Zhou, Shujun Hua, Yuan Lu, Ning Wen
  • Publication number: 20220216103
    Abstract: A method includes the following steps. A seed layer is formed over a structure having at least one semiconductor die. A first patterned photoresist layer is formed over the seed layer, wherein the first patterned photoresist layer includes a first opening exposing a portion of the seed layer. A metallic wiring is formed in the first opening and on the exposed portion of the seed layer. A second patterned photoresist layer is formed on the first patterned photoresist layer and covers the metallic wiring, wherein the second patterned photoresist layer includes a second opening exposing a portion of the metallic wiring. A conductive via is formed in the second opening and on the exposed portion of the metallic wiring. The first patterned photoresist layer and the second patterned photoresist layer are removed. The metallic wiring and the conductive via are laterally wrapped around with an encapsulant.
    Type: Application
    Filed: March 27, 2022
    Publication date: July 7, 2022
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Po-Yuan Teng, Bor-Rung Su, De-Yuan Lu, Hao-Yi Tsai, Tin-Hao Kuo, Tzung-Hui Lee, Tai-Min Chang
  • Patent number: 11370703
    Abstract: Described is a method of processing an antimicrobial glass substrate. More particularly, described is a method of removing one or more of silver nitrate or silver oxide on the surface of an antimicrobial glass substrate. Also described is a method of manufacturing a glass substrate that is substantially free of yellow discoloration.
    Type: Grant
    Filed: June 12, 2019
    Date of Patent: June 28, 2022
    Assignee: CORNING INCORPORATED
    Inventors: Tien San Chi, Chih Yuan Lu, Cheng-Da Tsai, Yu Ying Tsai, Shan Zhu
  • Patent number: 11359297
    Abstract: A method for electrolysis of water and a method for preparing a catalyst for electrolysis of water are provided. The method for electrolysis of water includes using a high entropy alloy as a catalyst. Further, the method for preparing a catalyst for electrolysis of water includes the steps of placing a substrate in an aqueous electrolyte containing a high entropy alloy precursor and performing an electroplating process on the substrate to form a high entropy alloy catalyst on the substrate.
    Type: Grant
    Filed: March 15, 2020
    Date of Patent: June 14, 2022
    Assignees: National Tsing Hua University, Chang Chun Plastics Co., Ltd., Chang Chun Petrochemical Co., Ltd., DAIREN CHEMICAL CORP.
    Inventors: Chun-Lung Huang, Shih-Yuan Lu
  • Patent number: 11355641
    Abstract: The present application provides a semiconductor device and the method of making the same. The method includes recessing a fin extending from a substrate, forming a base epitaxial feature on the recessed fin, forming a bar-like epitaxial feature on the base epitaxial feature, and forming a conformal epitaxial feature on the bar-like epitaxial feature. The forming of the bar-like epitaxial feature includes in-situ doping the bar-like epitaxial feature with an n-type dopant at a first doping concentration. The forming of the conformal epitaxial feature includes in-situ doping the conformal epitaxial feature with a second doping concentration greater than the first doping concentration.
    Type: Grant
    Filed: March 15, 2021
    Date of Patent: June 7, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Chun-An Lin, Wei-Yuan Lu, Feng-Cheng Yang, Tzu-Ching Lin, Li-Li Su
  • Patent number: 11334116
    Abstract: A screen protector comprises a glass-based substrate and an adhesive. The glass-based substrate comprises a first major surface, a second major surface, a thickness, and an edge. The first major surface comprises a first planar portion and a peripheral portion extending outwardly from the first planar portion. The second major surface comprises a second planar portion opposite the first planar portion and is parallel to the first planar portion. The edge comprises an outer peripheral surface that intersects the peripheral portion of the first major surface. The adhesive comprises a first major surface, a second major surface, a thickness, and an edge. The first major surface of the adhesive is adhered to the second major surface of the glass-based substrate.
    Type: Grant
    Filed: August 12, 2019
    Date of Patent: May 17, 2022
    Assignee: CORNING INCORPORATED
    Inventors: Sean Michael Buono, Jacob Immerman, Chih Yuan Lu, James Edward Morrison, Jr., Santona Pal, Ananthanarayanan Subramanian, Chu Yu Yeh
  • Publication number: 20220147080
    Abstract: A voltage regulator including an amplifier, a start signal generator and a power transistor is provided. The amplifier has a first positive input terminal, a second positive input terminal, and a negative input terminal to receive a start signal, a reference voltage and a feedback voltage respectively. An output terminal of the amplifier generates a driving voltage. The start signal generator is coupled to the first positive input terminal of the amplifier and generates the start signal, which is incremental, during a startup time interval in a voltage bypass mode. The power transistor generates an output voltage according to the driving voltage based on an operating power. In the voltage bypass mode, the reference voltage is equal to the operating power. A soft-start effect can be effectively achieved by the voltage regulator in the voltage bypass mode.
    Type: Application
    Filed: November 4, 2021
    Publication date: May 12, 2022
    Applicant: ALi Corporation
    Inventors: Chih-Yuan Hsu, Chien-Yuan Lu
  • Publication number: 20220142438
    Abstract: A detection assembly, a robotic vacuum cleaner, a walking floor status detection method and a control method are provided. The detection assembly includes optical transmitters, one optical receiver and an assembly body. The optical transmitters and the optical receiver are all mounted on the assembly body, and optical transmitters, the one receiver and the assembly body are integrated into one piece.
    Type: Application
    Filed: October 23, 2019
    Publication date: May 12, 2022
    Inventors: Yuan CHEN, Xiaowei XU, Linghua CHEN, Xianmin WEI, Shijie LI, Yuan LU
  • Patent number: 11329159
    Abstract: A field effect transistor includes a substrate and spacers over the substrate. The field effect transistor includes a channel recess cavity between the spacers, wherein a bottom-most surface of the channel recess cavity is parallel to the substrate top surface. The field effect transistor includes a gate stack, wherein the gate stack includes a bottom portion in the channel recess cavity and a top portion outside the channel recess cavity, the gate stack further includes a gate dielectric layer extending from the channel recess cavity along sidewalls of each of the pair of spacers, and the gate dielectric layer directly contacts the substrate below substrate top surface. The field effect transistor includes a strained source/drain (S/D) below the substrate top surface, wherein the strained S/D extends below the gate stack. The field effect transistor further includes a source/drain (S/D) extension substantially conformably surrounding the strained S/D.
    Type: Grant
    Filed: July 14, 2020
    Date of Patent: May 10, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Chun-Fai Cheng, Ka-Hing Fung, Li-Ping Huang, Wei-Yuan Lu
  • Publication number: 20220131014
    Abstract: A semiconductor structure and a method of forming the same are provided. A semiconductor structure according to the present disclosure includes a first channel member and a second channel member disposed over the first channel member, a first channel extension feature coupled to the first channel member, a second channel extension feature coupled to the second channel member, and an inner spacer feature disposed between the first channel extension feature and the second channel extension feature.
    Type: Application
    Filed: October 27, 2020
    Publication date: April 28, 2022
    Inventors: Wei-Jen Lai, Wei-Yuan Lu, Chih-Hao Yu, Chia-Pin Lin
  • Publication number: 20220130961
    Abstract: A method of semiconductor fabrication includes providing a semiconductor structure having a substrate and first, second, third, and fourth fins above the substrate. The method further includes forming an n-type epitaxial source/drain (S/D) feature on the first and second fins, forming a p-type epitaxial S/D feature on the third and fourth fins, and performing a selective etch process on the semiconductor structure to remove upper portions of the n-type epitaxial S/D feature and the p-type epitaxial S/D feature such that more is removed from the n-type epitaxial S/D feature than the p-type epitaxial S/D feature.
    Type: Application
    Filed: January 10, 2022
    Publication date: April 28, 2022
    Inventors: I-Wen Wu, Chen-Ming Lee, Fu-Kai Yang, Mei-Yun Wang, Chun-An Lin, Wei-Yuan Lu, Guan-Ren Wang, Peng Wang
  • Publication number: 20220121120
    Abstract: A photoresist apparatus and a method are provided. The photoresist apparatus includes a pre-baking apparatus. The pre-baking apparatus includes: a hot-plate, a first cover over the hot-plate, a second cover over the first cover, a first heating element extending along a topmost surface of the first cover, and a second heating element extending along a topmost surface of the second cover.
    Type: Application
    Filed: January 3, 2022
    Publication date: April 21, 2022
    Inventors: Hung-Jui Kuo, De-Yuan Lu, Chen-Hua Yu, Ming-Tan Lee
  • Patent number: 11289373
    Abstract: A method includes the following steps. A seed layer is formed over a structure having at least one semiconductor die. A first patterned photoresist layer is formed over the seed layer, wherein the first patterned photoresist layer includes a first opening exposing a portion of the seed layer. A metallic wiring is formed in the first opening and on the exposed portion of the seed layer. A second patterned photoresist layer is formed on the first patterned photoresist layer and covers the metallic wiring, wherein the second patterned photoresist layer includes a second opening exposing a portion of the metallic wiring. A conductive via is formed in the second opening and on the exposed portion of the metallic wiring. The first patterned photoresist layer and the second patterned photoresist layer are removed. The metallic wiring and the conductive via are laterally wrapped around with an encapsulant.
    Type: Grant
    Filed: July 7, 2019
    Date of Patent: March 29, 2022
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Po-Yuan Teng, Bor-Rung Su, De-Yuan Lu, Hao-Yi Tsai, Tin-Hao Kuo, Tzung-Hui Lee, Tai-Min Chang
  • Patent number: D947103
    Type: Grant
    Filed: October 25, 2019
    Date of Patent: March 29, 2022
    Assignee: FEDERAL CORPORATION
    Inventor: Chang-Yuan Lu