Abstract: A semiconductor structure and method for fabricating a semiconductor structure includes using two separate oxide layers to improve device reliability. A first oxide layer is formed adjacent a fin (e.g. a fin of a fin field-effect transistor (FinFET) device), a dummy gate is formed adjacent the first oxide layer, the dummy gate is removed, and a second oxide layer is then formed adjacent the first oxide layer. The use of the second oxide layer can improve device reliability by covering any damage that may be inflicted on the first oxide layer when the dummy gate is removed.

Abstract: Various embodiments of the present disclosure are directed towards a trench capacitor with a trench pattern for yield improvement. The trench capacitor is on a substrate and comprises a plurality of capacitor segments. The capacitor segments extend into the substrate according to the trench pattern and are spaced with a pitch on an axis. The plurality of capacitor segments comprises an edge capacitor segment at an edge of the trench capacitor and a center capacitor segment at a center of the trench capacitor. The edge capacitor segment has a greater width than the center capacitor segment and/or the pitch is greater at the edge capacitor segment than at the center capacitor segment. The greater width may facilitate stress absorption and the greater pitch may increase substrate rigidity at the edge of the trench capacitor where thermal expansion stress is greatest, thereby reducing substrate bending and trench burnout for yield improvements.

Abstract: Depositing a side slab structure on a cladding layer before etching a supporting dielectric prevents tapering of a silicon waveguide during etching of the supporting dielectric and a substrate. For example, the side slab structure may be deposited over the silicon waveguide and the cladding layer after etching the cladding layer. As a result, when an electronic device is integrated ex situ on the substrate, wave intensity and/or total internal reflection is improved, which improves an efficiency of the electronic device.

Abstract: Provided are a silicon carbide crystal growth device and a quality control method. The device includes: an annealing unit, a crystal growth unit, an atmosphere control unit, and a transport system; the atmosphere control unit provides a gas environment with low water, oxygen and nitrogen; the transport system transports a plurality of target objects after high-temperature purification by the annealing unit to the atmosphere control unit; after assembling silicon carbide seed crystal and silicon carbide powder in a graphite crucible and covering with thermal insulation material to form a container inside the atmosphere control unit, the transport system transports the container to the crystal growth unit. The method uses a weighing system in a chamber of the crystal growth unit to detect a weight change of silicon carbide seed crystal and silicon carbide powder during a crystal growth process through a plurality of weight sensors of the weighing system.

Abstract: Various embodiments of the present disclosure are directed towards a trench capacitor with a trench pattern for yield improvement. The trench capacitor is on a substrate and comprises a plurality of capacitor segments. The capacitor segments extend into the substrate according to the trench pattern and are spaced with a pitch on an axis. The plurality of capacitor segments comprises an edge capacitor segment at an edge of the trench capacitor and a center capacitor segment at a center of the trench capacitor. The edge capacitor segment has a greater width than the center capacitor segment and/or the pitch is greater at the edge capacitor segment than at the center capacitor segment. The greater width may facilitate stress absorption and the greater pitch may increase substrate rigidity at the edge of the trench capacitor where thermal expansion stress is greatest, thereby reducing substrate bending and trench burnout for yield improvements.

Abstract: A semiconductor structure includes a first device and a second device. The first device includes a plurality of first fins, a first work function layer over the plurality of first fins, and a first contact layer over the first work function layer. The second device includes a plurality of second fins, a second work function layer and the first work function layer over the plurality of the second fins, and a second contact layer over the first work function layer and the second work function layer. A distance between a bottom surface of the first work function layer and a bottom surface of the first contact layer is greater than a distance between a side surface of the first work function layer of the first device and a side surface of the first contact layer.

Abstract: A method of applying and then removing a protective layer over a portion of a gate stack is provided. The protective layer is deposited and then a plasma precursor is separated into components. Neutral radicals are then utilized in order to remove the protective layer. In some embodiments the removal also forms a protective by-product which helps to protect underlying layers from damage during the etching process.

Abstract: Depositing a side slab structure on a cladding layer before etching a supporting dielectric prevents tapering of a silicon waveguide during etching of the supporting dielectric and a substrate. For example, the side slab structure may be deposited over the silicon waveguide and the cladding layer after etching the cladding layer. As a result, when an electronic device is integrated ex situ on the substrate, wave intensity and/or total internal reflection is improved, which improves an efficiency of the electronic device.

Abstract: 1. A semiconductor structure includes a first fin; an isolation structure adjacent the first fin; a dielectric layer adjacent the isolation structure; a first oxide layer adjacent the first fin, the isolation structure, and the dielectric layer, and a second oxide layer adjacent the first oxide layer. The first oxide layer and the second oxide layer define a composite oxide layer. A horizontal portion of the composite oxide layer is thicker than a vertical portion of the composite oxide layer.

Abstract: A method includes: receiving a substrate; depositing a first gate layer over the substrate; patterning the first gate layer to form a first gate stack and leaving at least one void exposed from a sidewall of the first gate stack; depositing a dielectric layer on the sidewall of the first gate stack; and removing a first portion of the dielectric layer from the sidewall of the first gate stack while leaving a second portion of the dielectric layer to fill the at least one void.

Abstract: A method for forming a semiconductor structure includes following operations. A substrate is provided. The substrate has fin structures and includes a material having a substrate thermal expansion coefficient. A first dielectric material is formed over the substrate and the fin structures. The first dielectric material has a first thermal expansion coefficient. A second dielectric material is formed over the first dielectric material. The second dielectric material has a second thermal expansion coefficient. The second dielectric material is recessed to form an isolation structure between the fin structures.

Abstract: A semiconductor structure and method of manufacturing a semiconductor structure are provided. The method includes receiving a substrate with fin features; forming a first gate stack over the substrate, wherein the first gate stack comprise at least one void exposed from a surface of the first gate stack; forming a fill material in the at least one void; partially removing the fill material outside the at least one void, wherein a portion of the fill material is left in the at least one void; forming sidewall spacers besides the first gate stack; removing the first gate stack; and forming a second gate stack.

Abstract: A semiconductor structure and method for manufacturing the same are provided. The semiconductor structure includes a substrate having fin structures. The substrate includes a material having a substrate thermal expansion coefficient. The semiconductor structure also includes an isolation structure between the fin structures. The isolation structure includes a first dielectric material and a second dielectric material. The first dielectric material has a first thermal expansion coefficient and the second dielectric material has a second thermal expansion coefficient. The substrate thermal expansion coefficient is in between the first thermal expansion coefficient and the second thermal expansion coefficient.

Abstract: Various embodiments of the present disclosure are directed towards a trench capacitor with a trench pattern for yield improvement. The trench capacitor is on a substrate and comprises a plurality of capacitor segments. The capacitor segments extend into the substrate according to the trench pattern and are spaced with a pitch on an axis. The plurality of capacitor segments comprises an edge capacitor segment at an edge of the trench capacitor and a center capacitor segment at a center of the trench capacitor. The edge capacitor segment has a greater width than the center capacitor segment and/or the pitch is greater at the edge capacitor segment than at the center capacitor segment. The greater width may facilitate stress absorption and the greater pitch may increase substrate rigidity at the edge of the trench capacitor where thermal expansion stress is greatest, thereby reducing substrate bending and trench burnout for yield improvements.

Abstract: A method of making a semiconductor device includes depositing a TiN layer over a substrate. The method further includes doping a first portion of the TiN layer using an oxygen-containing plasma treatment. The method further includes doping a second portion of the TiN layer using a nitrogen-containing plasma treatment, wherein the second portion of the TiN layer directly contacts the first portion of the TiN layer. The method further includes forming a first metal gate electrode over the first portion of the TiN layer. The method further includes forming a second metal gate electrode over the second portion of the TiN layer, wherein the first metal gate electrode has a different work function from the second metal gate electrode, and the second metal gate electrode directly contacts the first metal gate electrode.

Abstract: A method includes forming a polymer layer on a patterned photo resist. The polymer layer extends into an opening in the patterned photo resist. The polymer layer is etched to expose the patterned photo resist. The polymer layer and a top Bottom Anti-Reflective Coating (BARC) are etched to pattern the top BARC, in which the patterned photo resist is used as an etching mask. The top BARC is used as an etching mask to etching an underlying layer.

Abstract: Various embodiments of the present disclosure are directed towards a trench capacitor with a trench pattern for yield improvement. The trench capacitor is on a substrate and comprises a plurality of capacitor segments. The capacitor segments extend into the substrate according to the trench pattern and are spaced with a pitch on an axis. The plurality of capacitor segments comprises an edge capacitor segment at an edge of the trench capacitor and a center capacitor segment at a center of the trench capacitor. The edge capacitor segment has a greater width than the center capacitor segment and/or the pitch is greater at the edge capacitor segment than at the center capacitor segment. The greater width may facilitate stress absorption and the greater pitch may increase substrate rigidity at the edge of the trench capacitor where thermal expansion stress is greatest, thereby reducing substrate bending and trench burnout for yield improvements.

Abstract: Depositing a side slab structure on a cladding layer before etching a supporting dielectric prevents tapering of a silicon waveguide during etching of the supporting dielectric and a substrate. For example, the side slab structure may be deposited over the silicon waveguide and the cladding layer after etching the cladding layer. As a result, when an electronic device is integrated ex situ on the substrate, wave intensity and/or total internal reflection is improved, which improves an efficiency of the electronic device.

Abstract: A semiconductor structure includes a first device and a second device. The first device includes a plurality of first fins, a first work function layer over the plurality of first fins, and a first contact layer over the first work function layer. The second device includes a plurality of second fins, a second work function layer and the first work function layer over the plurality of the second fins, and a second contact layer over the first work function layer and the second work function layer. A distance between a bottom surface of the first work function layer and a bottom surface of the first contact layer is greater than a distance between a side surface of the first work function layer of the first device and a side surface of the first contact layer.

Abstract: A semiconductor structure is provided. The semiconductor structure includes fin structures, a gate structure across the fin structures, and a dielectric layer. The gate structure includes a work function layer over the gate dielectric layer, and a contact layer over the work function layer. A portion of the work function layer is located between the fin structures, and a top surface of the portion is higher than a top surface of the fin structures. A top surface of the work function layer and a top surface of the dielectric layer are substantially on a same level. A method for forming a semiconductor structure is also provided.