Abstract: A semiconductor structure is provided. The semiconductor structure includes fin structures, a gate structure across the fin structures, and a dielectric layer. The gate structure includes a work function layer over the gate dielectric layer, and a contact layer over the work function layer. A portion of the work function layer is located between the fin structures, and a top surface of the portion is higher than a top surface of the fin structures. A top surface of the work function layer and a top surface of the dielectric layer are substantially on a same level. A method for forming a semiconductor structure is also provided.

Abstract: A complementary metal-oxide-semiconductor (CMOS) semiconductor device includes a substrate. The CMOS semiconductor device further includes an isolation region in the substrate. The CMOS semiconductor device further includes a P-metal gate electrode extending over the isolation region, wherein the P-metal gate electrode includes a first function metal and a TiN layer doped with a first material. The CMOS semiconductor device further includes an N-metal gate electrode extending over the isolation region, wherein the N-metal gate electrode includes a second function metal and a TiN layer doped with a second material different from the first material, a portion of the P-metal gate electrode is between a portion of the N-metal gate electrode and the substrate, and a portion of the TiN layer doped with the second material is between the portion of the P-metal gate electrode and the substrate.

Abstract: A method includes forming a polymer layer on a patterned photo resist. The polymer layer extends into an opening in the patterned photo resist. The polymer layer is etched to expose the patterned photo resist. The polymer layer and a top Bottom Anti-Reflective Coating (BARC) are etched to pattern the top BARC, in which the patterned photo resist is used as an etching mask. The top BARC is used as an etching mask to etching an underlying layer.

Abstract: Various embodiments of the present disclosure are directed towards a trench capacitor with a trench pattern for yield improvement. The trench capacitor is on a substrate and comprises a plurality of capacitor segments. The capacitor segments extend into the substrate according to the trench pattern and are spaced with a pitch on an axis. The plurality of capacitor segments comprises an edge capacitor segment at an edge of the trench capacitor and a center capacitor segment at a center of the trench capacitor. The edge capacitor segment has a greater width than the center capacitor segment and/or the pitch is greater at the edge capacitor segment than at the center capacitor segment. The greater width may facilitate stress absorption and the greater pitch may increase substrate rigidity at the edge of the trench capacitor where thermal expansion stress is greatest, thereby reducing substrate bending and trench burnout for yield improvements.

Abstract: A semiconductor structure is provided. The semiconductor structure includes fin structures and a gate structure across the fin structures. The gate structure includes a gate dielectric layer over fin structures, a work function layer over the gate dielectric layer, and a contact layer over the work function layer. In some embodiments, a portion of the work function layer is located between the fin structures, and a top surface of the portion is higher than a top surface of the fin structures. A method for forming a semiconductor structure is also provided.

Abstract: A semiconductor structure and method of manufacturing a semiconductor structure are provided. The method includes receiving a substrate with fin features; forming sacrificial gate stacks over the substrate; forming a sacrificial fill layer over the sacrificial gate stacks; removing the sacrificial fill layer; forming sidewall spacers besides the sacrificial gate stacks; removing the sacrificial gate stacks; and forming metal gate stacks; wherein the sacrificial fill layers is made of fill materials with a high etch rate selectivity to materials of the sidewall spacers.

Abstract: A semiconductor structure and method for manufacturing the same are provided. The semiconductor structure includes a substrate having fin structures. The substrate includes a material having a substrate thermal expansion coefficient. The semiconductor structure also includes an isolation structure between the fin structures. The isolation structure includes a first dielectric material and a second dielectric material. The first dielectric material has a first thermal expansion coefficient and the second dielectric material has a second thermal expansion coefficient. The substrate thermal expansion coefficient is in between the first thermal expansion coefficient and the second thermal expansion coefficient.

Abstract: A semiconductor structure is provided. The semiconductor structure includes fin structures and a gate structure across the fin structures. The gate structure includes a gate dielectric layer over fin structures, a work function layer over the gate dielectric layer, and a contact layer over the work function layer. In some embodiments, a portion of the work function layer is located between the fin structures, and a top surface of the portion is higher than a top surface of the fin structures. A method for forming a semiconductor structure is also provided.

Abstract: A method of applying and then removing a protective layer over a portion of a gate stack is provided. The protective layer is deposited and then a plasma precursor is separated into components. Neutral radicals are then utilized in order to remove the protective layer. In some embodiments the removal also forms a protective by-product which helps to protect underlying layers from damage during the etching process.

Abstract: A method of applying and then removing a protective layer over a portion of a gate stack is provided. The protective layer is deposited and then a plasma precursor is separated into components. Neutral radicals are then utilized in order to remove the protective layer. In some embodiments the removal also forms a protective by-product which helps to protect underlying layers from damage during the etching process.

Abstract: A method includes forming a polymer layer on a patterned photo resist. The polymer layer extends into an opening in the patterned photo resist. The polymer layer is etched to expose the patterned photo resist. The polymer layer and a top Bottom Anti-Reflective Coating (BARC) are etched to pattern the top BARC, in which the patterned photo resist is used as an etching mask. The top BARC is used as an etching mask to etching an underlying layer.

Abstract: A method includes forming a polymer layer on a patterned photo resist. The polymer layer extends into an opening in the patterned photo resist. The polymer layer is etched to expose the patterned photo resist. The polymer layer and a top Bottom Anti-Reflective Coating (BARC) are etched to pattern the top BARC, in which the patterned photo resist is used as an etching mask. The top BARC is used as an etching mask to etching an underlying layer.

Abstract: A method includes forming a polymer layer on a patterned photo resist. The polymer layer extends into an opening in the patterned photo resist. The polymer layer is etched to expose the patterned photo resist. The polymer layer and a top Bottom Anti-Reflective Coating (BARC) are etched to pattern the top BARC, in which the patterned photo resist is used as an etching mask. The top BARC is used as an etching mask to etching an underlying layer.

Abstract: A complementary metal-oxide-semiconductor (CMOS) semiconductor device includes a substrate. The CMOS semiconductor device further includes an isolation region in the substrate. The CMOS semiconductor device further includes a P-metal gate electrode extending over the isolation region, wherein the P-metal gate electrode includes a first function metal and a TiN layer doped with a first material. The CMOS semiconductor device further includes an N-metal gate electrode extending over the isolation region, wherein the N-metal gate electrode includes a second function metal and a TiN layer doped with a second material different from the first material, a portion of the P-metal gate electrode is between a portion of the N-metal gate electrode and the substrate, and a portion of the TiN layer doped with the second material is between the portion of the P-metal gate electrode and the substrate.

Abstract: A method of applying and then removing a protective layer over a portion of a gate stack is provided. The protective layer is deposited and then a plasma precursor is separated into components. Neutral radicals are then utilized in order to remove the protective layer. In some embodiments the removal also forms a protective by-product which helps to protect underlying layers from damage during the etching process.

Abstract: A CMOS semiconductor device includes a substrate comprising an isolation region separating a P-active region and an N-active region. The CMOS semiconductor device further includes a P-metal gate electrode over the P-active region and extending over the isolation region, wherein the P-metal gate electrode includes a P-work function metal and a doped TiN layer between the P-work function metal and substrate. The CMOS semiconductor device further includes an N-metal gate electrode over the N-active region and extending over the isolation region, wherein the N-metal gate electrode includes an N-work function metal and a nitrogen-rich TiN layer between the N-work function metal and substrate, wherein a portion of the P-metal gate electrode is between a portion of the N-metal gate electrode and the substrate.

Abstract: In a method of manufacturing a semiconductor device, a dummy gate structure is formed over a substrate. A first insulating layer is formed over the dummy gate structure. The dummy gate structure is removed so as to form a gate space in the first insulating layer. A first conductive layer is formed in the gate space so as to form a reduced gate space. The reduced gate space is filled with a second conductive layer made of a different material from the first conductive layer. The filled first conductive layer and the second conductive layer are recessed so as to form a first gate recess. A third conductive layer is formed over the first conductive layer and the second conductive layer in the first gate recess. After recessing the filled first conductive layer and the second conductive layer, the second conductive layer protrudes from the first conductive layer.

Abstract: A CMOS semiconductor device includes a substrate comprising an isolation region separating a P-active region and an N-active region. The CMOS semiconductor device further includes a P-metal gate electrode over the P-active region and extending over the isolation region, wherein the P-metal gate electrode includes a P-work function metal and a doped TiN layer between the P-work function metal and substrate. The CMOS semiconductor device further includes an N-metal gate electrode over the N-active region and extending over the isolation region, wherein the N-metal gate electrode includes an N-work function metal and a nitrogen-rich TiN layer between the N-work function metal and substrate, wherein a portion of the P-metal gate electrode is between a portion of the N-metal gate electrode and the substrate.

Abstract: A method of fabricating a semiconductor device includes forming a gate strip including a dummy electrode and a TiN layer. The method includes removing a first portion of the dummy electrode to form a first opening over a P-active region and an isolation region. The method includes performing an oxygen-containing plasma treatment on a first portion of the TiN layer; and filling the first opening with a first metal material. The method includes removing a second portion of the dummy electrode to form a second opening over an N-active region and the isolation region. The method includes performing a nitrogen-containing plasma treatment on a second portion of the TiN layer; and filling the second opening with a second metal material. The second portion of the TiN layer connects to the first portion of the TiN layer over the isolation region.

Abstract: A method includes providing a fin structure containing a semiconductor material. The method includes forming a gate dielectric layer over the fin structure, the gate dielectric layer being at least partially wrapped around the fin structure. The method includes forming a gate layer over the gate dielectric layer, wherein the gate layer is formed in a conformal manner. The method includes forming a dummy gate layer over the gate layer.