Patents by Inventor Yuan-Sheng Huang
Yuan-Sheng Huang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20180012806Abstract: In a method of manufacturing a semiconductor device, a dummy gate structure is formed over a substrate. A first insulating layer is formed over the dummy gate structure. The dummy gate structure is removed so as to form a gate space in the first insulating layer. A first conductive layer is formed in the gate space so as to form a reduced gate space. The reduced gate space is filled with a second conductive layer made of a different material from the first conductive layer. The filled first conductive layer and the second conductive layer are recessed so as to form a first gate recess. A third conductive layer is formed over the first conductive layer and the second conductive layer in the first gate recess. After recessing the filled first conductive layer and the second conductive layer, the second conductive layer protrudes from the first conductive layer.Type: ApplicationFiled: September 8, 2017Publication date: January 11, 2018Inventors: Po-Hsueh LI, Chih-Yang YEH, Chun-Chan HSIAO, Kuan-Lin YEH, Yuan-Sheng HUANG
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Patent number: 9779997Abstract: In a method of manufacturing a semiconductor device, a dummy gate structure is formed over a substrate. A first insulating layer is formed over the dummy gate structure. The dummy gate structure is removed so as to form a gate space in the first insulating layer. A first conductive layer is formed in the gate space so as to form a reduced gate space. The reduced gate space is filled with a second conductive layer made of a different material from the first conductive layer. The filled first conductive layer and the second conductive layer are recessed so as to form a first gate recess. A third conductive layer is formed over the first conductive layer and the second conductive layer in the first gate recess. After recessing the filled first conductive layer and the second conductive layer, the second conductive layer protrudes from the first conductive layer.Type: GrantFiled: March 11, 2016Date of Patent: October 3, 2017Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Po-Hsueh Li, Chih-Yang Yeh, Chun-Chan Hsiao, Kuan-Lin Yeh, Yuan-Sheng Huang
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Publication number: 20170194209Abstract: In a method of manufacturing a semiconductor device, a dummy gate structure is formed over a substrate. A first insulating layer is formed over the dummy gate structure. The dummy gate structure is removed so as to form a gate space in the first insulating layer. A first conductive layer is formed in the gate space so as to form a reduced gate space. The reduced gate space is filled with a second conductive layer made of a different material from the first conductive layer. The filled first conductive layer and the second conductive layer are recessed so as to form a first gate recess. A third conductive layer is formed over the first conductive layer and the second conductive layer in the first gate recess. After recessing the filled first conductive layer and the second conductive layer, the second conductive layer protrudes from the first conductive layer.Type: ApplicationFiled: March 11, 2016Publication date: July 6, 2017Inventors: Po-Hsueh LI, Chih-Yang YEH, Chun-Chan HSIAO, Kuan-Lin YEH, Yuan-Sheng HUANG
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Publication number: 20170186853Abstract: A method of fabricating a semiconductor device includes forming a gate strip including a dummy electrode and a TiN layer. The method includes removing a first portion of the dummy electrode to form a first opening over a P-active region and an isolation region. The method includes performing an oxygen-containing plasma treatment on a first portion of the TiN layer; and filling the first opening with a first metal material. The method includes removing a second portion of the dummy electrode to form a second opening over an N-active region and the isolation region. The method includes performing a nitrogen-containing plasma treatment on a second portion of the TiN layer; and filling the second opening with a second metal material. The second portion of the TiN layer connects to the first portion of the TiN layer over the isolation region.Type: ApplicationFiled: March 13, 2017Publication date: June 29, 2017Inventors: Ming ZHU, Hui-Wen LIN, Harry Hak-Lay CHUANG, Bao-Ru YOUNG, Yuan-Sheng HUANG, Ryan Chia-Jen CHEN, Chao-Cheng CHEN, Kuo-Cheng CHING, Ting-Hua HSIEH, Carlos H. DIAZ
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Patent number: 9613819Abstract: Process chambers and methods of preparing and operating a process chamber are disclosed. In some embodiments, a method of preparing a process chamber for processing a substrate includes: forming a first barrier layer over an element disposed within a cavity of the process chamber, the element comprising an outgassing material; and forming, within the process chamber, a second barrier layer over the first barrier layer.Type: GrantFiled: June 6, 2014Date of Patent: April 4, 2017Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Yu Chao Lin, Ming-Ching Chang, Yuan-Sheng Huang, Jui-Ming Chen, Chao-Cheng Chen
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Patent number: 9595443Abstract: The invention relates to integrated circuit fabrication, and more particularly to a metal gate structure. An exemplary structure for a CMOS semiconductor device comprises a substrate comprising an isolation region surrounding and separating a P-active region and an N-active region; a P-metal gate electrode over the P-active region and extending over the isolation region, wherein the P-metal gate electrode comprises a P-work function metal and an oxygen-containing TiN layer between the P-work function metal and substrate; and an N-metal gate electrode over the N-active region and extending over the isolation region, wherein the N-metal gate electrode comprises an N-work function metal and a nitrogen-rich TiN layer between the N-work function metal and substrate, wherein the nitrogen-rich TiN layer connects to the oxygen-containing TiN layer over the isolation region.Type: GrantFiled: October 20, 2011Date of Patent: March 14, 2017Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Ming Zhu, Hui-Wen Lin, Harry-Hak-Lay Chuang, Bao-Ru Young, Yuan-Sheng Huang, Ryan Chia-Jen Chen, Chao-Cheng Chen, Kuo-Cheng Ching, Ting-Hua Hsieh, Carlos H. Diaz
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Patent number: 9536980Abstract: An embodiment device includes a gate stack extending over a semiconductor substrate, a hard mask disposed on a top surface of the gate stack, and a low-k dielectric spacer on a side of the gate stack. A top of the low-k dielectric spacer is lower than an upper surface of the hard mask. The device further includes a contact electrically connected to a source/drain region adjacent the gate stack. The contact extends laterally over the low-k dielectric spacer, and a dielectric material is disposed between the contact and the low-k dielectric spacer. The dielectric material has a higher selectivity to etching than the low-k dielectric spacer.Type: GrantFiled: July 28, 2015Date of Patent: January 3, 2017Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Yuan-Sheng Huang, Chao-Cheng Chen, Chun-Hung Lee, Hua Feng Chen, Po-Hsueh Li
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Publication number: 20160181398Abstract: A method includes providing a fin structure containing a semiconductor material. The method includes forming a gate dielectric layer over the fin structure, the gate dielectric layer being at least partially wrapped around the fin structure. The method includes forming a gate layer over the gate dielectric layer, wherein the gate layer is formed in a conformal manner. The method includes forming a dummy gate layer over the gate layer.Type: ApplicationFiled: March 2, 2016Publication date: June 23, 2016Inventors: Yuan-Sheng Huang, Chao-Cheng Chen, Ryan Chia-Jen Chen, Ming-Ching Chang, Tzu-Yen Hsieh
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Patent number: 9287179Abstract: The present disclosure involves a FinFET. The FinFET includes a fin structure formed over a substrate. A gate dielectric layer is least partially wrapped around a segment of the fin structure. The gate dielectric layer contains a high-k gate dielectric material. The FinFET includes a polysilicon layer conformally formed on the gate dielectric layer. The FinFET includes a metal gate electrode layer formed over the polysilicon layer. The present disclosure provides a method of fabricating a FinFET. The method includes providing a fin structure containing a semiconductor material. The method includes forming a gate dielectric layer over the fin structure, the gate dielectric layer being at least partially wrapped around the fin structure. The method includes forming a polysilicon layer over the gate dielectric layer, wherein the polysilicon layer is formed in a conformal manner. The method includes forming a dummy gate layer over the polysilicon layer.Type: GrantFiled: January 19, 2012Date of Patent: March 15, 2016Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Yuan-Sheng Huang, Tzu-Yen Hsieh, Ming-Ching Chang, Chao-Cheng Chen, Chia-Jen Chen
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Publication number: 20150357164Abstract: Process chambers and methods of preparing and operating a process chamber are disclosed. In some embodiments, a method of preparing a process chamber for processing a substrate includes: forming a first barrier layer over an element disposed within a cavity of the process chamber, the element comprising an outgassing material; and forming, within the process chamber, a second barrier layer over the first barrier layer.Type: ApplicationFiled: June 6, 2014Publication date: December 10, 2015Inventors: Yu Chao Lin, Ming-Ching Chang, Yuan-Sheng Huang, Jui-Ming Chen, Chao-Cheng Chen
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Patent number: 9147679Abstract: A method of fabricating a semiconductor integrated circuit (IC) is disclosed. The method includes receiving a semiconductor device, patterning a first hard mask to form a first recess in a high-resistor (Hi-R) stack, removing the first hard mask, forming a second recess in the Hi-R stack, forming a second hard mask in the second recess in the Hi-R stack. A HR can then be formed in the semiconductor substrate by the second hard mask and a gate trench etch.Type: GrantFiled: March 31, 2014Date of Patent: September 29, 2015Assignee: Taiwan Semiconductor Manufacturing Company, ltd.Inventors: Tzu-Yen Hsieh, Ming-Ching Chang, Yuan-Sheng Huang, Ming-Chia Tai, Chao-Cheng Chen
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Publication number: 20140284724Abstract: A method of fabricating a semiconductor integrated circuit (IC) is disclosed. The method includes receiving a semiconductor device, patterning a first hard mask to form a first recess in a high-resistor (Hi-R) stack, removing the first hard mask, forming a second recess in the Hi-R stack, forming a second hard mask in the second recess in the Hi-R stack. A HR can then be formed in the semiconductor substrate by the second hard mask and a gate trench etch.Type: ApplicationFiled: March 31, 2014Publication date: September 25, 2014Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Tzu-Yen Hsieh, Ming-Ching Chang, Yuan-Sheng Huang, Ming-Chia Tai, Chao-Cheng Chen
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Patent number: 8691655Abstract: A method of fabricating a semiconductor integrated circuit (IC) is disclosed. The method includes receiving a semiconductor device, patterning a first hard mask to form a first recess in a high-resistor (Hi-R) stack, removing the first hard mask, forming a second recess in the Hi-R stack, forming a second hard mask in the second recess in the Hi-R stack. A HR can then be formed in the semiconductor substrate by the second hard mask and a gate trench etch.Type: GrantFiled: May 15, 2012Date of Patent: April 8, 2014Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Tzu-Yen Hsieh, Ming-Ching Chang, Yuan-Sheng Huang, Ming-Chia Tai, Chao-Cheng Chen
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Publication number: 20130309834Abstract: A method of fabricating a semiconductor integrated circuit (IC) is disclosed. The method includes receiving a semiconductor device, patterning a first hard mask to form a first recess in a high-resistor (Hi-R) stack, removing the first hard mask, forming a second recess in the Hi-R stack, forming a second hard mask in the second recess in the Hi-R stack. A HR can then be formed in the semiconductor substrate by the second hard mask and a gate trench etch.Type: ApplicationFiled: May 15, 2012Publication date: November 21, 2013Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Tzu-Yen Hsieh, Ming-Ching Chang, Yuan-Sheng Huang, Ming-Chia Tai, Chao-Cheng Chen
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Patent number: 8507979Abstract: A method of fabricating a semiconductor integrated circuit (IC) is disclosed. The method includes providing a semiconductor substrate and forming a gate trench therein. The method also includes filling in the gate trench partially with a work-function (WF) metal stack, and filling in the remaining gate trench with a dummy-filling-material (DFM) over the WF metal stack. A sub-gate trench is formed by etching-back the WF metal stack in the gate trench, and is filled with an insulator cap to form an isolation region in the gate trench. The DFM is fully removed to from a MG-center trench (MGCT) in the gate trench, which is filled with a fill metal.Type: GrantFiled: July 31, 2012Date of Patent: August 13, 2013Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Yuan-Sheng Huang, Ming-Ching Chang, Chao-Cheng Chen
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Publication number: 20130187235Abstract: The present disclosure involves a FinFET. The FinFET includes a fin structure formed over a substrate. A gate dielectric layer is least partially wrapped around a segment of the fin structure. The gate dielectric layer contains a high-k gate dielectric material. The FinFET includes a polysilicon layer conformally formed on the gate dielectric layer. The FinFET includes a metal gate electrode layer formed over the polysilicon layer. The present disclosure provides a method of fabricating a FinFET. The method includes providing a fin structure containing a semiconductor material. The method includes forming a gate dielectric layer over the fin structure, the gate dielectric layer being at least partially wrapped around the fin structure. The method includes forming a polysilicon layer over the gate dielectric layer, wherein the polysilicon layer is formed in a conformal manner. The method includes forming a dummy gate layer over the polysilicon layer.Type: ApplicationFiled: January 19, 2012Publication date: July 25, 2013Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Yuan-Sheng Huang, Tzu-Yen Hsieh, Ming-Ching Chang, Chao-Cheng Chen, Chia-Jen Chen
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Publication number: 20130099323Abstract: The invention relates to integrated circuit fabrication, and more particularly to a metal gate structure. An exemplary structure for a CMOS semiconductor device comprises a substrate comprising an isolation region surrounding and separating a P-active region and an N-active region; a P-metal gate electrode over the P-active region and extending over the isolation region, wherein the P-metal gate electrode comprises a P-work function metal and an oxygen-containing TiN layer between the P-work function metal and substrate; and an N-metal gate electrode over the N-active region and extending over the isolation region, wherein the N-metal gate electrode comprises an N-work function metal and a nitrogen-rich TiN layer between the N-work function metal and substrate, wherein the nitrogen-rich TiN layer connects to the oxygen-containing TiN layer over the isolation region.Type: ApplicationFiled: October 20, 2011Publication date: April 25, 2013Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Ming ZHU, Hui-Wen LIN, Harry-Hak-Lay CHUANG, Bao-Ru YOUNG, Yuan-Sheng HUANG, Ryan Chia-Jen CHEN, Chao-Cheng CHEN
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Patent number: 7940480Abstract: An optical transmission device including a driving unit having a transmitting member, a guide member, a frame, a clipping unit and a flexible member is disclosed. The clipping unit has a main clip engaging with one side of the transmitting member, and a sub-clip engaging with the other side of the transmitting member. The flexible member pushes the main clip to the sub-clip, so that the sub-clip radially and axially approaches the transmitting member.Type: GrantFiled: July 2, 2009Date of Patent: May 10, 2011Assignee: Asia Optical Co., Inc.Inventor: Yuan-Sheng Huang
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Publication number: 20100232014Abstract: An optical transmission device including a driving unit having a transmitting member, a guide member, a frame, a clipping unit and a flexible member is disclosed. The clipping unit has a main clip engaging with one side of the transmitting member, and a sub-clip engaging with the other side of the transmitting member. The flexible member pushes the main clip to the sub-clip, so that the sub-clip radially and axially approaches the transmitting member.Type: ApplicationFiled: July 2, 2009Publication date: September 16, 2010Applicant: ASIA OPTICAL CO., INC.Inventor: Yuan-Sheng Huang
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Publication number: 20030082920Abstract: Chamber-reversed dry etching is disclosed. A semiconductor dry etching system can include a plasma chamber, a wafer lifter, a wafer chuck, and a bias supply. Polymer is introduced into the plasma chamber, such that excess polymer forms and subsequently peels off the inner vertical walls of the chamber, and falls down due to gravity. The wafer lifter holds the semiconductor wafer upside-down over the plasma chamber, preventing the excess polymer from falling onto the wafer. The wafer chuck moves the wafer upside-down to over the plasma chamber for the wafer lifter to hold the wafer upside-down over the plasma chamber. The bias supply biases the wafer, such that the polymer is electro-statically attracted to the wafer.Type: ApplicationFiled: November 1, 2001Publication date: May 1, 2003Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Yuan-sheng Huang, Hsin-Yi Chen