Abstract: The present invention provides compositions comprising optimized ratios of Red clover phytoestrogens as determined by a proprietary physiologically based pharmacokinetic and pharmacodynamic model. The compositions are useful for modulating, preventing or treating postmenopausal or climacteric symptoms, which include but are not limited to bone loss, bone remodeling, hot flushes and vaginal atrophy. The present invention also provides methods for modulating, preventing or treating postmenopausal or climacteric symptoms using the compositions disclosed herein.

Abstract: An apparatus includes a memory controller configured to apply selected one or ones of the program verify voltage levels to a single tier of memory cells. A memory controller is configured to: program data into the plurality of memory cells; and perform a program verify operation across multiple voltage levels with a first voltage level of the program verify operation being applied to a single tier that represents all of the tiers in the memory group and a second voltage level of the program verify operation being applied to multiple tiers, wherein the first voltage level is less than the second voltage level. In embodiments, less than all of the tiers, e.g.

Abstract: Apparatus and methods are described to program memory cells and verify stored values programmed into the cells. The next stage in stored memory can be moved to the current verification iteration when certain conditions are met. Verification can include counting bits that exceed a voltage value for a stage being verified to produce a bit count number and determining if the bit count number for the stage being verified meets a threshold value. If the bit count number does not meet the threshold, the verification process can continue with a current verify iteration and thereafter move to a next verify iteration. If the bit count number does meet the threshold, the process can add a next stage to the current verify iteration and thereafter move to a next verify iteration.

Abstract: Power and/or current regulation in non-volatile memory systems is disclosed. Peak power/current usage may be reduced by staggering concurrent program operations in the different semiconductor dies. Each set of one or more semiconductor dies has an earliest permitted start time for its program operation, as well as a number of permitted backup start times. The permitted start times are unique for each set of one or more semiconductor dies. There may be a uniform gap or delay between each permitted start time. If a semiconductor die is busy with another memory operation at or after its earliest permitted start time, then the program operation is initiated or resumed at one of the permitted backup times. By having permitted backup times, the memory system need not poll each semiconductor die to determine whether the semiconductor die is ready/busy in order to determine when a die should start a program operation.

Abstract: A memory device disclosed herein. The memory device comprises: a memory string including a first select transistor, a memory cell transistor, and a second select transistor connected in series; a bit line connected to one end of the first select transistor; a source line connected to one end of the second select transistor; a first select line connected to a gate of the first select transistor; a word line connected to a gate of the memory cell transistor; a second select line connected to a gate of the second select transistor; and a control circuit configured to perform, before a program operation, a pre-charge operation comprising: applying a voltage to the second select line connected to the gate of the second select transistor to cause gate-induced drain leakage from the second select transistor.

Abstract: An apparatus includes a controller and a plurality of memory dies operable connected to and controlled by the controller. Each of the memory dies draws a current from a current source during a program operation. The controller being configured to receive a clock signal from each of the memory dies; count the number of clock signal received to determine a count value; and dynamically stagger at least one of the memory dies relative to the other memory dies when the count value reaches a maximum count value within a threshold time. The controller operates to dynamically stagger operation of at least one memory die to prevent the group of memory dies from operating synchronously.

Abstract: An apparatus, disclosed herein, comprises a plurality of planes, each plane of the plurality of planes including a plurality of memory cells and a control circuit coupled to the plurality of memory cells. The control circuit is configured to: determine a position of a program loop in a sequence of program loops performed to complete a programming operation; initiate an inhibit bit line ramping event for the first plane including ramping of a set of bit lines of a first plane up to an inhibit voltage and based on the position of the program loop, initiate an inhibit bit line ramping event with a ramping start time delay for a second plane, where the inhibit bit line ramping event for the second plane includes initiating ramping of a set of bit lines of the second plane up to the inhibit voltage after the ramping start time delay.

Abstract: An apparatus, disclosed herein, comprises a plurality of planes, each plane of the plurality of planes including a plurality of memory cells and a control circuit coupled to the plurality of memory cells. The control circuit is configured to: determine a position of a program loop in a sequence of program loops performed to complete a programming operation; initiate an inhibit bit line ramping event for the first plane including ramping of a set of bit lines of a first plane up to an inhibit voltage and based on the position of the program loop, initiate an inhibit bit line ramping event with a ramping start time delay for a second plane, where the inhibit bit line ramping event for the second plane includes initiating ramping of a set of bit lines of the second plane up to the inhibit voltage after the ramping start time delay.

Abstract: A memory device disclosed herein. The memory device comprises: a memory string including a first select transistor, a memory cell transistor, and a second select transistor connected in series; a bit line connected to one end of the first select transistor; a source line connected to one end of the second select transistor; a first select line connected to a gate of the first select transistor; a word line connected to a gate of the memory cell transistor; a second select line connected to a gate of the second select transistor; and a control circuit configured to perform, before a program operation, a pre-charge operation comprising: applying a voltage to the second select line connected to the gate of the second select transistor to cause gate-induced drain leakage from the second select transistor.

Abstract: A storage device including control circuitry, communicatively coupled to a non-volatile memory, configured to perform a programming operation to program a set of memory cells. The control circuitry, when performing the programming operation, may be configured to apply a set of biased program voltages to lines connecting to respective memory cells in an array. The set of biased program voltages may have values that are based on positions of the respective memory cells within the array relative to an outer memory string group of a set of memory string groups.

Abstract: Aspects of a storage device including a memory and a controller are provided which allow for reduction of current during program operations using pre-charge timing control based on an inhibit bit line count acquired from data latches. When the inhibit bit line count is within a bit line count range, the controller pre-charges bit lines in memory during a first time period to a first target voltage, and when the inhibit bit line count is outside the bit line count range, the controller pre-charges the bit lines during a second, earlier time period to a second, smaller target voltage. The controller is thus configured to reduce current and minimize operation overlaps in the earlier time period during the middle of the program operation where current is highest. Thus, a balance in power consumption and performance may be achieved during program operations using timing control.

Abstract: Aspects of a storage device including a memory and a controller are provided which allow for reduction of current in open blocks during read operations using multi-stage read voltage control. The controller determines whether a block is open or closed. If the block is closed, the controller causes a read voltage to be applied to one of the block's word lines. If the block is open, the controller causes a read voltage to be applied to another of the block's word lines in a number of stages. The controller further causes a read voltage to be applied to another word line of the open block in a different number of stages. Thus, read voltages for open blocks may ramp in multiple stages in contrast to read voltages for closed blocks, as well as ramp in different numbers of stages for different word lines in open blocks.

Abstract: Aspects of a storage device including a memory and a controller are provided which allow for reduction of current during program operations using pre-charge ramp rate control based on an inhibit bit line count acquired from data latches. When the inhibit bit line count is within a bit line count range, the controller pre-charges bit lines in memory at a first ramp rate to a first target voltage, and when the inhibit bit line count is outside the bit line count range, the controller pre-charges the bit lines at a second, faster ramp rate to a second, smaller target voltage. The inhibit bit line count may increase throughout a program operation, and the bit line count range may be configured for the middle of the program operation where current is typically high. Thus, a balance in power consumption and performance may be achieved during program operations using ramp rate control.

Abstract: Aspects of a storage device including a memory and a controller are provided which allow for reduction of current in open blocks during read operations using read voltage ramp rate control. The controller determines whether a block is open or closed. If the block is closed, the controller causes a read voltage to be applied to one of the block's word lines at a first ramp rate. If the block is open, the controller causes a read voltage to be applied to another of the block's word lines at a slower, second ramp rate. The controller further causes a read voltage to be applied to another word line of the open block at a different, third ramp rate. Thus, read voltages for open blocks may ramp slower than read voltages for closed blocks, as well as ramp at different rates for different word lines in open blocks.

Abstract: A memory apparatus and method of operation is provided. The apparatus includes a block of memory cells arranged in strings and connected to word lines overlying one another in a stack. The block is divided into first and second sub-blocks programmed as a whole in a sub-block mode and includes a particular group connected to a particular word line. A control circuit determines whether the particular group being read is in the second sub-block when operating in the sub-block mode. The control circuit also determines whether one of the first and second sub-blocks is not programmed based on whether the particular group being read is in the second sub-block. The control circuit applies an adjusted read voltage to the word lines of the one of the first and second sub-blocks while reading the particular group based on whether the one of the first and second sub-blocks is not programmed.

Abstract: Aspects of a storage device including a memory and a controller are provided which allow for reduction of current in open blocks during read operations using multi-stage read voltage control. The controller determines whether a block is open or closed. If the block is closed, the controller causes a read voltage to be applied to one of the block's word lines. If the block is open, the controller causes a read voltage to be applied to another of the block's word lines in a number of stages. The controller further causes a read voltage to be applied to another word line of the open block in a different number of stages. Thus, read voltages for open blocks may ramp in multiple stages in contrast to read voltages for closed blocks, as well as ramp in different numbers of stages for different word lines in open blocks.

Abstract: A respiratory protection mask includes detachably connected main body and front cover. The main body includes a shielding member for shielding a wearer's mouth and nose, and has air outlet with air-outlet valve and air inlets with air-inlet valves. The mask is characterized in a guide structure and a limiting structure provided between the main body and the front cover. The guide structure includes corresponding slide rail and slide channel capable of guiding the front cover to move along a linear path parallel to a longitudinal section of the air outlet to assemble to the main body and cover the air-outlet valve. The limiting structure includes corresponding male and female fasteners that are detachably engaged with each other when the front cover is assembled to the main body, preventing the front cover from moving in an opposite direction on the linear path to separate from the main body.

Abstract: A storage device is disclosed herein. The storage device comprises a block including a plurality of memory cells and a circuit coupled to the plurality of memory cells of the block. The circuit is configured to program memory cells of a plurality of strings of a word line of the block and verify, for a plurality of sets of the memory cells, a data state of a set of the memory cells, where each set of the plurality of sets of the memory cells includes a memory cell from each string of the plurality of strings of the word line. Further, the circuit is configured to determine a number of sets of the plurality of memory cell sets that are verified to be in a first data state and determine, based on the number of sets, whether the block is faulty.

Abstract: An electric vehicle parking energy supply system includes at least one electric power control unit that is connected with at least one electric power generation system, a parking tower having multiple vehicle carrying platforms that are movable in multiple axes for receiving electric vehicles to park thereon, multiple power buses, a power charging control unit arranged on each vehicle carrying platform for connection with and charging the electric vehicle, and at least one electric vehicle charging management center. The power charging control unit controls bidirectional electric energy supply for supplying working power required by the parking tower, the vehicle carrying platforms, and the power buses and selling extra power back to a commercial power supply. The power buses are arranged longitudinally to each correspond to one side of a predetermined location of each of the vehicle carrying platforms of the parking tower.

Abstract: A method for programming a target memory cell of a memory array of a non-volatile memory system, the method comprising performing a read operation of one or more memory cells neighboring a target memory cell, thereby determining a data pattern of the one or more neighboring memory cells, storing the data pattern and, during a program operation of the target memory cell, adjusting a verify voltage level according to the stored data pattern of the one or more neighboring memory cells.