Patents by Inventor Yuan TSENG

Yuan TSENG has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20230381260
    Abstract: The present invention provides compositions comprising optimized ratios of Red clover phytoestrogens as determined by a proprietary physiologically based pharmacokinetic and pharmacodynamic model. The compositions are useful for modulating, preventing or treating postmenopausal or climacteric symptoms, which include but are not limited to bone loss, bone remodeling, hot flushes and vaginal atrophy. The present invention also provides methods for modulating, preventing or treating postmenopausal or climacteric symptoms using the compositions disclosed herein.
    Type: Application
    Filed: August 10, 2023
    Publication date: November 30, 2023
    Inventors: Yun Kau TAM, Yi-Chan James Lin, Brian Duff Sloley, Chih-Yuan Tseng
  • Publication number: 20230366879
    Abstract: This invention relates to a surface coating for capture circulating rare cells, comprising a nonfouling composition to prevent the binding of non-specific cells and adsorption of serum components; a bioactive composition for binding the biological substance, such as circulating tumor cells; with or without a linker composition that binds the nonfouling and bioactive compositions. The invention also provide a surface coating for capture and purification of a biological substance, comprising a releasable composition to release the non-specific cells and other serum components; a bioactive composition for binding the biological substance, such as circulating tumor cells; with or without a linker composition that binds the releasable and bioactive compositions. The present invention also discloses a novel microfluidic chip, with specific patterned microstructures to create a flow disturbance and increase the capture rate of the biological substance.
    Type: Application
    Filed: April 27, 2023
    Publication date: November 16, 2023
    Inventors: Ying-Chih Chang, Han-Chung Wu, Po-Yuan Tseng, Jen-Chia Wu
  • Publication number: 20230368852
    Abstract: A non-volatile memory device includes a control circuit configured to connect to a bit line that is connected to one or more non-volatile memory cells. The control circuit includes a first plurality of data latches connected to a first local data bus to store first program-verify pass/fail bits and a second plurality of data latches connected to a second local data bus to store second program-verify pass/fail bits for second non-volatile memory cells. The non-volatile memory device further includes a shared isolation latch and one or more interface circuits connected to the first local data bus and the second local data bus. The one or more interface circuits are configured to selectively block the first program-verify pass/fail bits from the first plurality of latches and the second program-verify pass/fail bits from the second plurality of latches according to an indicator bit stored in the shared isolation latch.
    Type: Application
    Filed: May 16, 2022
    Publication date: November 16, 2023
    Applicant: SanDisk Technologies LLC
    Inventors: Kei Kitamura, Iris Lu, Tai-Yuan Tseng
  • Publication number: 20230360696
    Abstract: A read is initiated with respect to a target cell. A pair of adjacent cells includes a first cell and a second cell each adjacent to the target cell. First cell state information is obtained for the first cell and second cell state information is obtained for the second cell. A state information bin is determined by applying a pre-defined operation to the first cell state information and the second cell state information of the respective pair of adjacent cells. The target cell is assigned to the state information bin. Each state information bin defines a read level offset for reading the target cell.
    Type: Application
    Filed: May 2, 2023
    Publication date: November 9, 2023
    Inventors: Huai-Yuan Tseng, Akira Goda, Ching-Huang Lu, Eric N. Lee, Tomoharu Tanaka
  • Publication number: 20230360705
    Abstract: A method includes causing a first set of memory cells, associated with a first wordline of a memory array, to be programmed with a first set of threshold voltage distributions; causing a second set of memory cells, associated with a second wordline adjacent to the first wordline, to be programmed with a second set of threshold voltage distributions; after programming the second set of cells, causing the first set of memory cells to be coarse programmed with an intermediate third set of threshold voltage distributions that is at least twice in number compared to the first set; and causing the first set of memory cells to be fine programmed with a final third set of threshold voltage distributions. At least some threshold voltage distributions of the final third set of threshold voltage distributions have wider read window margins than those of the intermediate third set of threshold voltage distributions.
    Type: Application
    Filed: April 24, 2023
    Publication date: November 9, 2023
    Inventors: Huai-Yuan Tseng, Giovanni Maria Paolucci, Kishore Kumar Muchherla, James Fitzpatrick, Akira Goda
  • Patent number: 11798631
    Abstract: Read and write circuitry, described herein, comprises data latches, each data latch connected to a bit line and arranged in a same column as the bit line; and transfer latches, each transfer latch connected to a data latch and arranged in a same column as the data latch. Further, circuitry described herein is configured to: transfer a word to and from the transfer latches of a first column and the subset of transfer latches of a second column; transfer a first portion of the word between the transfer latches of the first column and data latches of the first column that are connected to the transfer latches of the first column; and transfer a second portion of the word between the subset of transfer latches and data latches of the second column that are connected to the subset of transfer latches.
    Type: Grant
    Filed: October 21, 2021
    Date of Patent: October 24, 2023
    Assignee: SanDisk Technologies LLC
    Inventors: Iris Lu, Tai-Yuan Tseng
  • Publication number: 20230335201
    Abstract: A method includes causing a read operation to be initiated with respect to a set of target cells. For each target cell, a respective group of adjacent cells is adjacent to the target cell. The method further includes obtaining, for each group of adjacent cells, respective cell state information, assigning, based on the cell state information, each target cell of the set of target cells to a respective state information bin, and determining a set of calibrated read level offsets. Each state information bin is associated with a respective group of target cells of the set of target cells, and each calibrated read level offset of the set of calibrated read level offsets is associated with a respective state information bin of the set of state information bins.
    Type: Application
    Filed: April 18, 2023
    Publication date: October 19, 2023
    Inventors: Tomoharu Tanaka, James Fitzpatrick, Huai-Yuan Tseng, Kishore Kumar Muchherla, Eric N. Lee, David Scott Ebsen, Dung Viet Nguyen, Akira Goda
  • Patent number: 11790992
    Abstract: The storage device includes a non-volatile memory with control circuitry and an array of memory cells that are arranged in a plurality of word lines. The control circuitry is configured to program the memory cells in a plurality of programming loops which include applying a programming pulse to a selected word line to program at least one memory cell of the selected word line to a programmed data state. The programming loops also include simultaneously applying a verify pulse to the selected word line to verify a data state being programmed, applying a first voltage to at least one unselected word line that has not been programmed, and applying a second voltage to at least one unselected word line that has already been programmed. The first voltage is determined as a function of the programmed data state to reduce a voltage threshold distribution across the memory cells.
    Type: Grant
    Filed: June 28, 2021
    Date of Patent: October 17, 2023
    Assignee: SanDisk Technologies LLC
    Inventors: Yu-Chung Lien, Huai-yuan Tseng
  • Publication number: 20230326531
    Abstract: Technology is disclosed herein for a memory system having a dynamic supply voltage to sense amplifiers. In an aspect, the supply voltage has a higher magnitude when charging inhibited bit lines during a program operation and a lower magnitude when verifying/sensing memory cells. Reducing the magnitude of the supply voltage saves power and/or current. However, if the lower magnitude were used when the inhibited bit lines are charged during the program operations, some of the memory cells that should be inhibited from programming might experience at least some programming. Using the higher magnitude supply voltage during bit line charging of the program operation assures that the inhibited bit lines are charged to a sufficient voltage to keep drain side select gates of NAND strings off so that the NAND channel will boost properly to inhibit programming of such memory cells.
    Type: Application
    Filed: April 11, 2022
    Publication date: October 12, 2023
    Applicant: SanDisk Technologies LLC
    Inventors: Yanjie Wang, Ohwon Kwon, Kou Tei, Tai-Yuan Tseng, Yasue Yamamoto, Yonggang Wu, Guirong Liang
  • Patent number: 11758718
    Abstract: A three-dimensional memory device includes an alternating stack of insulating layers and electrically conductive layers, first memory opening fill structures extending through the alternating stack and including a respective first vertical semiconductor channel having a tubular section and a semi-tubular section, second memory opening fill structures, first bit lines electrically connected to a respective subset of the first drain regions, second bit lines electrically connected to a respective subset of the second drain regions, and an erase voltage application circuit configured to electrically bias the first bit lines at a first bit line erase voltage and the second bit lines at a second bit line erase voltage during an erase operation. The first bit line erase voltage is greater than the second bit line erase voltage.
    Type: Grant
    Filed: July 14, 2021
    Date of Patent: September 12, 2023
    Assignee: SANDISK TECHNOLOGIES LLC
    Inventors: Yu-Chung Lien, Abhijith Prakash, Keyur Payak, Jiahui Yuan, Huai-Yuan Tseng, Shinsuke Yada, Kazuki Isozumi
  • Publication number: 20230247817
    Abstract: A method (of manufacturing fins for a semiconductor device) includes: forming semiconductor fins including ones thereof having a first cap with a first etch sensitivity (first capped fins) and second ones thereof having a second cap with a second etch sensitivity (second capped fins), the first and second etch sensitivities being different; and eliminating selected ones of the first capped fins and selected ones of the second capped fins.
    Type: Application
    Filed: March 27, 2023
    Publication date: August 3, 2023
    Inventors: Chih-Liang CHEN, Chih-Ming LAI, Charles Chew-Yuen YOUNG, Chin-Yuan TSENG, Jiann-Tyng TZENG, Kam-Tou SIO, Ru-Gun LIU, Wei-Liang LIN, L. C. CHOU
  • Patent number: 11699494
    Abstract: A method for programming a memory block of a non-volatile memory structure, wherein the method provides, during a program verify operation, selecting only a partial segment of memory cells of a memory block for bit scan mode, applying a sensing bias voltage to one or more bit lines of the memory block associated with the selected memory cells, and initiating a bit scan mode of the selected memory cells.
    Type: Grant
    Filed: June 7, 2021
    Date of Patent: July 11, 2023
    Inventors: Xue Bai Pitner, Yu-Chung Lien, Deepanshu Dutta, Huai-yuan Tseng, Ravi Kumar
  • Publication number: 20230207022
    Abstract: A local data bus of a sense amplifier associated with one bit line is used to perform logical operations for a sensing operation performed by another sense amplifier associated with a different bit line. Each sense amplifier circuit includes a sensing node that is pre-charged, then discharged through a selected memory cell and a local data bus with a number of data latches connected. Target program data can be stored in the latches and combined in logical combinations with the sensed value of the memory cell to determine whether it has verified. By including a transfer circuit between the local data buses of a pair of sense amplifiers, the logical operations of a first sense amplifier can be performed using the local data bus of the paired sense amplifier, freeing the first sense amplifier's sense node to be concurrently pre-charged for a subsequent sensing operation, thereby improving performance.
    Type: Application
    Filed: December 27, 2021
    Publication date: June 29, 2023
    Applicant: SanDisk Technologies LLC
    Inventors: Iris Lu, Tai-Yuan Tseng, Chia-Kai Chou
  • Patent number: 11688870
    Abstract: A fuel cell energy circulative utilization system includes an input energy, a first electric cell having an electricity output terminal and an energy output terminal, a second electric cell having an electricity input terminal, an energy input terminal, and an energy output terminal, and an energy circulation control device connected among the first and second electric cells and the input energy. The input energy includes an energy source containing hydrocarbons or hydrogen and connected to an energy input port of the first electric cell in order to make the first electric cell outputs electricity through the electricity output terminal and energy products of thermal energy and water through the energy output terminal.
    Type: Grant
    Filed: July 21, 2021
    Date of Patent: June 27, 2023
    Assignee: Electric Energy Express Corporation
    Inventor: Ling-Yuan Tseng
  • Patent number: 11674958
    Abstract: This invention relates to a surface coating for capture circulating rare cells, comprising a nonfouling composition to prevent the binding of non-specific cells and adsorption of serum components; a bioactive composition for binding the biological substance, such as circulating tumor cells; with or without a linker composition that binds the nonfouling and bioactive compositions. The invention also provide a surface coating for capture and purification of a biological substance, comprising a releasable composition to release the non-specific cells and other serum components; a bioactive composition for binding the biological substance, such as circulating tumor cells; with or without a linker composition that binds the releasable and bioactive compositions. The present invention also discloses a novel microfluidic chip, with specific patterned microstructures to create a flow disturbance and increase the capture rate of the biological substance.
    Type: Grant
    Filed: March 27, 2020
    Date of Patent: June 13, 2023
    Assignee: Academia Sinica
    Inventors: Ying-Chih Chang, Han-Chung Wu, Po-Yuan Tseng, Jen-Chia Wu
  • Publication number: 20230146549
    Abstract: A memory device with one or more planes having sub-blocks is disclosed. The memory device may further include a voltage switch transistor for each of sub-blocks. Additionally, the memory device may further include a row decoder for each of sub-blocks. As a result, an operation to two sub-blocks can be performed at different times. For example, using a row decoder and voltage switch transistor, a sub-block can be initially read, followed by a subsequent read of another sub-block using a separate row decoder and voltage switch transistor. By staggering the read operations through a time delay, the peak current Icc associated with the supply voltage can be reduced.
    Type: Application
    Filed: November 9, 2021
    Publication date: May 11, 2023
    Applicant: SanDisk Technologies LLC
    Inventors: Yu-Chung Lien, Deepanshu Dutta, Tai-Yuan Tseng
  • Publication number: 20230130365
    Abstract: Read and write circuitry, described herein, comprises data latches, each data latch connected to a bit line and arranged in a same column as the bit line; and transfer latches, each transfer latch connected to a data latch and arranged in a same column as the data latch. Further, circuitry described herein is configured to: transfer a word to and from the transfer latches of a first column and the subset of transfer latches of a second column; transfer a first portion of the word between the transfer latches of the first column and data latches of the first column that are connected to the transfer latches of the first column; and transfer a second portion of the word between the subset of transfer latches and data latches of the second column that are connected to the subset of transfer latches.
    Type: Application
    Filed: October 21, 2021
    Publication date: April 27, 2023
    Applicant: SanDisk Technologies LLC
    Inventors: Iris Lu, Tai-Yuan Tseng
  • Patent number: 11636905
    Abstract: A memory apparatus and method of operation is provided. The apparatus includes a block having memory cells connected to word lines and arranged in strings and is divided into a first sub-block and a second sub-block each configured to be erased as a whole in an erase operation. The apparatus has a temperature measuring circuit configured to detect an ambient temperature of the apparatus. A control circuit is configured to determine a word line inhibit voltage based on the ambient temperature. The control circuit applies an erase voltage to each of the strings while simultaneously applying a word line erase voltage to the word lines associated with a selected one of the first and second sub-blocks to encourage erasing and the word line inhibit voltage to the word lines associated with an unselected one of the first and second sub-blocks to discourage erasing in the erase operation.
    Type: Grant
    Filed: December 7, 2020
    Date of Patent: April 25, 2023
    Assignee: SanDisk Technologies LLC
    Inventors: Sarath Puthenthermadam, Huai-yuan Tseng
  • Publication number: 20230111546
    Abstract: An image processing device includes a three-dimensional noise reduction (3D NR) circuit, an artificial intelligence noise reduction (AI NR) circuit, a weight determination circuit and an image blending circuit. The 3D NR circuit performs a 3D NR operation on input image data to generate first image data. The AI NR circuit performs an AI NR operation on the input image data to generate second image data. The weight determination circuit outputs a blending weight according to a motion index. The image blending circuit blends the first image data and the second image data according to the blending weight to generate output image data.
    Type: Application
    Filed: March 30, 2022
    Publication date: April 13, 2023
    Inventors: Hsiu-Wei HO, Chien-Yuan TSENG, Ho-Tai TSAI
  • Publication number: 20230104397
    Abstract: A selective EMI shielding structure for a semiconductor package and a method of fabrication thereof is disclosed. The semiconductor package, comprising: a substrate having a first face; at least one first electronic component mounted adjacent to a first region of the first face; a least one second electronic component mounted adjacent to a second region of the first face; and an encapsulant disposed over the first and the second electronic components, wherein the encapsulant covers directly over the first electronic component, and wherein the encapsulant covers the second electronic component through a layer of conductive material.
    Type: Application
    Filed: October 1, 2021
    Publication date: April 6, 2023
    Applicant: Advanced Semiconductor Engineering, Inc.
    Inventors: Meng-Jen WANG, Chien-Yuan TSENG, Hung Chen KUO, Ying-Hao WEI, Chia-Feng HSU, Yuan-Long CHIAO