Patents by Inventor Yuan TSENG

Yuan TSENG has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11616067
    Abstract: In an embodiment, a method (of manufacturing fins for a semiconductor device) includes: forming a first layer (on a semiconductor substrate) that has first spacers and etch stop layer (ESL) portions which are interspersed; forming second spacers on central regions of the first spacers and the ESL portions; removing exposed regions of the first spacers and the ESL portions and corresponding underlying portions of the semiconductor substrate; removing the second spacers resulting in corresponding first capped semiconductor fins and second capped semiconductor fins that are organized into first and second sets; each member of the first set having a first cap with a first etch sensitivity; and each member of the second set having a second cap with a different second etch sensitivity; and eliminating selected ones of the first capped semiconductor fins and selected ones of the second capped semiconductor fins.
    Type: Grant
    Filed: December 16, 2021
    Date of Patent: March 28, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Chih-Liang Chen, Chih-Ming Lai, Charles Chew-Yuen Young, Chin-Yuan Tseng, Jiann-Tyng Tzeng, Kam-Tou Sio, Ru-Gun Liu, Wei-Liang Lin, L. C. Chou
  • Patent number: 11606305
    Abstract: A quality of service adjusting method based on application categories is configured to adjust a Quality of Service (QoS) of a communication device. A network session processing step is performed to drive a hardware accelerator to process a plurality of network sessions. A packet receiving step is performed to drive a processing unit to receive a first packet group of each of the network sessions. A packet analyzing step is performed to execute a packet inspecting module to analyze a plurality of packet data of the first packet group of each of the network sessions, and to classify an application corresponding to each of the network sessions. A list establishing step is performed to establish a priority list. A bandwidth distributing step is performed to distribute a network bandwidth to a second packet group of each of the network sessions according to the priority list.
    Type: Grant
    Filed: July 28, 2021
    Date of Patent: March 14, 2023
    Assignee: WISTRON NEWEB CORPORATION
    Inventors: Li-Heng Su, Chuan-Yuan Tseng
  • Patent number: 11600343
    Abstract: Technology is disclosed for an efficient read NAND memory cells while mitigating read disturb. In an aspect, a read sequence includes a read spike that removes residual electrons from the NAND channels, followed by reading multiple different groups of memory cells, followed by a channel clean operation. The read spike and channel clean mitigate read disturb. The read spike and channel clean each take a significant amount of time to perform. However, since multiple groups of memory cells are read between the read spike and channel clean this time is essentially spread over the reading of multiple groups, thereby improving the average time to read a single group of memory cells. In one aspect, reading the multiple different groups of memory cells includes reading one or more pages from each of the groups of memory cells. In one aspect, each group is in a different sub-block.
    Type: Grant
    Filed: May 25, 2021
    Date of Patent: March 7, 2023
    Assignee: SanDisk Technologies LLC
    Inventors: Yu-Chung Lien, Tomer Eliash, Huai-Yuan Tseng
  • Publication number: 20230035723
    Abstract: The present disclosure provides methods of treating pancreatic cancer by administering a cationic liposomal formulation. Additional therapeutic agents or therapies may also be included.
    Type: Application
    Filed: February 24, 2022
    Publication date: February 2, 2023
    Applicant: SynCore Biotechnology Co., Ltd.
    Inventors: Ruey-Kuen Hsieh, Hui-Yuan Tseng, Sih-Ting Lin
  • Publication number: 20230016518
    Abstract: A three-dimensional memory device includes an alternating stack of insulating layers and electrically conductive layers, first memory opening fill structures extending through the alternating stack and including a respective first vertical semiconductor channel having a tubular section and a semi-tubular section, second memory opening fill structures, first bit lines electrically connected to a respective subset of the first drain regions, second bit lines electrically connected to a respective subset of the second drain regions, and an erase voltage application circuit configured to electrically bias the first bit lines at a first bit line erase voltage and the second bit lines at a second bit line erase voltage during an erase operation. The first bit line erase voltage is greater than the second bit line erase voltage.
    Type: Application
    Filed: July 14, 2021
    Publication date: January 19, 2023
    Inventors: Yu-Chung LIEN, Abhijith PRAKASH, Keyur PAYAK, Jiahui YUAN, Huai-Yuan TSENG, Shinsuke YADA, Kazuki ISOZUMI
  • Publication number: 20220415399
    Abstract: The storage device includes a non-volatile memory with control circuitry and an array of memory cells that are arranged in a plurality of word lines. The control circuitry is configured to program the memory cells in a plurality of programming loops which include applying a programming pulse to a selected word line to program at least one memory cell of the selected word line to a programmed data state. The programming loops also include simultaneously applying a verify pulse to the selected word line to verify a data state being programmed, applying a first voltage to at least one unselected word line that has not been programmed, and applying a second voltage to at least one unselected word line that has already been programmed. The first voltage is determined as a function of the programmed data state to reduce a voltage threshold distribution across the memory cells.
    Type: Application
    Filed: June 28, 2021
    Publication date: December 29, 2022
    Applicant: SanDisk Technologies LLC
    Inventors: Yu-Chung Lien, Huai-yuan Tseng
  • Publication number: 20220415415
    Abstract: Apparatuses and techniques are described for reducing the number of latches used in sense circuits for a memory device. The number of internal user data latches in a sense circuit is reduced by using an external data transfer latch to store a bit of user data, in place of an internal user data latch. The user data in the data transfer latches identifies a subset of the data states which are not prohibited from having a verify test. The subset is shifted as the program operation proceeds, at specified program loops, to encompass higher data states. The completion of programming by a memory cell is indicated by the user data latches and another internal latch of the sense circuit in place of the external data transfer latch.
    Type: Application
    Filed: June 23, 2021
    Publication date: December 29, 2022
    Applicant: SanDisk Technologies LLC
    Inventors: Tai-Yuan Tseng, Chia-Kai Chou, Iris Lu
  • Patent number: 11539643
    Abstract: Systems and methods of instant-messaging bot for robotic process automation (RPA) and robotic textual-content extraction from digital images include a chatbot application, a software RPA manager, and an instant-messaging (IM) platform, all built for an enterprise. The enterprise IM platform is connected to one or more public IM platforms over the Internet. The RPA manager contains multiple modules of enterprise workflows and receives instructions from the enterprise chatbot for executing individual workflows. The system allows enterprise users connected to the enterprise IM platform, and external users connected to the public IM platforms, to use instant messaging to initiate enterprise workflows that are automated with the help of the enterprise chatbot and delivered via instant messaging. Furthermore, textual-content extraction from digital images is incorporated in the RPA manager as an enterprise workflow, and provides improved convolutional neural network (CNN) methods for textual-content extraction.
    Type: Grant
    Filed: October 12, 2020
    Date of Patent: December 27, 2022
    Assignee: D8AI Inc.
    Inventors: Ping-Yuan Tseng, Chiou-Shann Fuh, Richard Li-Cheng Sheng, Hui Hsiung
  • Patent number: 11532482
    Abstract: A method of manufacturing a semiconductor device includes depositing a first material on a substrate, depositing on the substrate a second material that has an etch selectivity different from an etch selectively of the first material, depositing a spacer material on the first and second material, and etching the substrate using the spacer material as an etch mask to form a fin under the first material and a fin under the second material.
    Type: Grant
    Filed: February 9, 2021
    Date of Patent: December 20, 2022
    Assignee: Taiwan Semiconductor Manufacturing Company Limited
    Inventors: Lei-Chun Chou, Chih-Liang Chen, Chih-Ming Lai, Charles Chew-Yuen Young, Chin-Yuan Tseng, Hsin-Chih Chen, Shi Ning Ju, Jiann-Tyng Tzeng, Kam-Tou Sio, Ru-Gun Liu, Wei-Cheng Lin, Wei-Liang Lin
  • Patent number: 11532370
    Abstract: To improve programming performance for a non-volatile memory , the verification of multiple programming levels can be performed based on a single discharge of a sensing capacitor through a selected memory cell by using different voltage levels on a second plate of the sensing capacitor: after discharging a first plate of the sensing capacitor through the selected memory cell, a result amount of charge is trapped on the first plate, which is then used to set first and second control gate voltages on a sensing transistor whose control gate is connected to the first place of the sensing capacitor based on respectively setting the second plate of the sensing capacitor to first and second voltage levels. To further improve programming performance, when the non-volatile memory stores in a multistate format, after the next to highest data state finishes programming, the next programming pulse can use a larger step size.
    Type: Grant
    Filed: May 25, 2021
    Date of Patent: December 20, 2022
    Assignee: SanDisk Technologies LLC
    Inventors: Xiang Yang, Huai-Yuan Tseng, Deepanshu Dutta
  • Publication number: 20220392552
    Abstract: A method for programming a memory block of a non-volatile memory structure, wherein the method comprises, during a program verify operation, selecting only a partial segment of memory cells of a memory block for bit scan mode, applying a sensing bias voltage to one or more bit lines of the memory block associated with the selected memory cells, and initiating a bit scan mode of the selected memory cells.
    Type: Application
    Filed: June 7, 2021
    Publication date: December 8, 2022
    Applicant: SanDisk Technologies LLC
    Inventors: Xue Bai Pitner, Yu-Chung Lien, Deepanshu Dutta, Huai-Yuan Tseng, Ravi Kumar
  • Patent number: 11521677
    Abstract: A memory apparatus and method of operation are provided. The apparatus includes memory cells connected to word lines and arranged in strings and configured to retain a threshold voltage. A control circuit is coupled to the word lines and strings and is configured to compute a target word line voltage including a kicking voltage to be applied to selected ones of word lines for a kick time during a read operation. The control circuit extends the kick time by a compensation time to a compensated kick time in response to determining the target word line voltage is not greater than a predetermined voltage design limit. The control circuit applies the kicking voltage to the selected ones of word lines for the compensated kick time thereby enabling a word line voltage to reach one of a plurality of reference voltages quickly without exceeding the predetermined voltage design limit.
    Type: Grant
    Filed: May 21, 2021
    Date of Patent: December 6, 2022
    Assignee: SanDisk Technologies LLC
    Inventors: Xiang Yang, Huai-yuan Tseng
  • Patent number: 11521686
    Abstract: A memory apparatus and method of operation is provided. The apparatus includes memory cells connected to word lines and bit lines and configured to retain a threshold voltage corresponding to one of a plurality of data states following a program operation. A control circuit is coupled to the word lines and the bit lines. The control circuit is configured to count a bit-scan quantity of the memory cells during a bit-scan of the program operation. The control circuit determines whether the bit-scan quantity of the plurality of memory cells is greater than at least one predetermined bit-scan threshold. In response to the bit-scan quantity of the memory cells being greater than the at least one predetermined bit-scan threshold, the control circuit is configured to adjust a word line ramp rate of a word line voltage applied to the word lines during the program operation.
    Type: Grant
    Filed: March 31, 2021
    Date of Patent: December 6, 2022
    Assignee: SanDisk Technologies LLC
    Inventors: Yu-Chung Lien, Hua-Ling Hsu, Huai-Yuan Tseng, Fanglin Zhang
  • Publication number: 20220383961
    Abstract: Technology is disclosed for an efficient read NAND memory cells while mitigating read disturb. In an aspect, a read sequence includes a read spike that removes residual electrons from the NAND channels, followed by reading multiple different groups of memory cells, followed by a channel clean operation. The read spike and channel clean mitigate read disturb. The read spike and channel clean each take a significant amount of time to perform. However, since multiple groups of memory cells are read between the read spike and channel clean this time is essentially spread over the reading of multiple groups, thereby improving the average time to read a single group of memory cells. In one aspect, reading the multiple different groups of memory cells includes reading one or more pages from each of the groups of memory cells. In one aspect, each group is in a different sub-block.
    Type: Application
    Filed: May 25, 2021
    Publication date: December 1, 2022
    Applicant: SanDisk Technologies LLC
    Inventors: Yu-Chung Lien, Tomer Eliash, Huai-Yuan Tseng
  • Publication number: 20220384190
    Abstract: A method for forming a semiconductor device structure is provided. The method includes forming a first spacer over a substrate. The method includes partially removing the first spacer to form a gap dividing the first spacer into a first part and a second part. The method includes forming a filling layer covering a first top surface and a first sidewall of the first spacer. The filling layer and the first spacer together form a strip structure. The method includes forming a second spacer over a second sidewall of the strip structure. The method includes forming a third spacer over a third sidewall of the second spacer. The third spacer is narrower than the second spacer.
    Type: Application
    Filed: August 9, 2022
    Publication date: December 1, 2022
    Inventors: Chih-Ming LAI, Shih-Ming CHANG, Wei-Liang LIN, Chin-Yuan TSENG, Ru-Gun LIU
  • Publication number: 20220383965
    Abstract: To improve programming performance for a non-volatile memory , the verification of multiple programming levels can be performed based on a single discharge of a sensing capacitor through a selected memory cell by using different voltage levels on a second plate of the sensing capacitor: after discharging a first plate of the sensing capacitor through the selected memory cell, a result amount of charge is trapped on the first plate, which is then used to set first and second control gate voltages on a sensing transistor whose control gate is connected to the first place of the sensing capacitor based on respectively setting the second plate of the sensing capacitor to first and second voltage levels. To further improve programming performance, when the non-volatile memory stores in a multistate format, after the next to highest data state finishes programming, the next programming pulse can use a larger step size.
    Type: Application
    Filed: May 25, 2021
    Publication date: December 1, 2022
    Applicant: SanDisk Technologies LLC
    Inventors: Xiang Yang, Huai-Yuan Tseng, Deepanshu Dutta
  • Patent number: 11514991
    Abstract: A method for detecting and isolating defective memory plane(s) of a non-volatile memory structure during a program verify operation, comprising: initiating, for each plane, a word line verify voltage level scan with a bit scan pass fail criterion and at a starting voltage located within an intended program threshold voltage distribution curve, incrementally decreasing the word line verify voltage by a predetermined offset until a specific condition of the scan is obtained, and storing the voltage at which the specific condition of the scan is obtained, wherein the stored voltage represents a voltage of an upper tail portion of an actual programmed threshold voltage distribution curve of the plane. The stored voltages of all of the memory planes of the structure are compared to determine which plane corresponds to the lowest stored voltage. A “fail” status is applied to the plane corresponding to the lowest stored voltage.
    Type: Grant
    Filed: May 4, 2021
    Date of Patent: November 29, 2022
    Assignee: SanDisk Technologies LLC
    Inventors: Fanqi Wu, Hua-Ling Hsu, Deepanshu Dutta, Huai-yuan Tseng
  • Publication number: 20220375515
    Abstract: A memory apparatus and method of operation are provided. The apparatus includes memory cells connected to word lines and arranged in strings and configured to retain a threshold voltage. A control circuit is coupled to the word lines and strings and is configured to compute a target word line voltage including a kicking voltage to be applied to selected ones of word lines for a kick time during a read operation. The control circuit extends the kick time by a compensation time to a compensated kick time in response to determining the target word line voltage is not greater than a predetermined voltage design limit. The control circuit applies the kicking voltage to the selected ones of word lines for the compensated kick time thereby enabling a word line voltage to reach one of a plurality of reference voltages quickly without exceeding the predetermined voltage design limit.
    Type: Application
    Filed: May 21, 2021
    Publication date: November 24, 2022
    Applicant: SanDisk Technologies LLC
    Inventors: Xiang Yang, Huai-yuan Tseng
  • Patent number: 11508450
    Abstract: Aspects of a storage device including a memory and a controller are provided. The memory can include memory dies that draw a current from a current source during a program operation. The controller may monitor for an alarm signal from the memory dies on a first common channel between the controller and the memory dies. The alarm signal indicates that a corresponding memory die is entering an operational state that draws a peak current from the current source for the program operation. The controller can receive, from the memory dies, one or more alarm signals on the first common channel within a predetermined threshold time. The controller can transmit a postpone signal on a second common channel to the memory dies based on the one or more alarm signals received within the predetermined threshold time.
    Type: Grant
    Filed: June 18, 2021
    Date of Patent: November 22, 2022
    Assignee: WESTERN DIGITAL TECHNOLOGIES, INC.
    Inventors: Yu-Chung Lien, Huai-Yuan Tseng, Deepanshu Dutta
  • Publication number: 20220367201
    Abstract: A method of reducing corner rounding during patterning of a substrate to form a prescribed pattern comprising a corner includes dividing the pattern into a first pattern and a second pattern, the first pattern forming a first edge of the corner and the second pattern forming a second edge of the corner. At least a portion of the second pattern overlaps the first pattern such that the first edge intersects with the second edge to form a corner of the prescribed pattern. The method further includes forming the first pattern in a first mask layer disposed on a substrate to expose the substrate and forming the second pattern in the first mask layer to expose the substrate. The substrate exposed through the first mask layer is then etched to obtain the pattern.
    Type: Application
    Filed: July 25, 2022
    Publication date: November 17, 2022
    Inventors: Chin-Yuan TSENG, Yu-Tien SHEN, Wei-Liang LIN, Chih-Ming LAI, Kuo-Cheng CHING, Shi-Ning JU, Li-Te LIN, Ru-Gun LIU