Patents by Inventor Yuan Xiao

Yuan Xiao has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20150034906
    Abstract: A semiconductor device and a method for fabricating the same are disclosed. In the method, a substrate structure is provided, including a substrate and a fin-shaped buffer layer formed on the surface of the substrate. A QW material layer is formed on the surface of the fin-shaped buffer layer. A barrier material layer is formed on the QW material layer. The QW material layer is suitable for forming an electron gas therein. Thereby the short-channel effect is improved, while high mobility of the semiconductor device is guaranteed. In addition, according to the present disclosure, thermal dissipation of the semiconductor device may be improved, and thus performance and stability of the device may be improved.
    Type: Application
    Filed: May 19, 2014
    Publication date: February 5, 2015
    Applicant: SEMICONDUCTOR MANUFACTURING INTERNATIONAL (SHANGHAI) CORPORATION
    Inventor: De Yuan XIAO
  • Publication number: 20150034905
    Abstract: A method of fabricating a semiconductor device is provided. The method includes forming a substrate structure, wherein the substrate structure includes a substrate and a fin-shaped barrier layer formed on a surface of the substrate; forming a quantum well (QW) material layer on a surface of the fin-shaped barrier layer; and forming a barrier material layer on the QW material layer.
    Type: Application
    Filed: April 29, 2014
    Publication date: February 5, 2015
    Applicant: SEMICONDUCTOR MANUFACTURING INTERNATIONAL (SHANGHAI) CORPORATION
    Inventor: De Yuan XIAO
  • Publication number: 20150024559
    Abstract: A system and method for integrated circuits with surrounding gate structures are disclosed. The integrated circuits system includes a transistor having a gate all around cylindrical (GAAC) nanowire channel with an interposed dielectric layer. The cylindrical nanowire channel being in a middle section of a semiconductor wire pattern connects the source and drain region positioned at the two opposite end sections of the same wire pattern.
    Type: Application
    Filed: October 9, 2014
    Publication date: January 22, 2015
    Inventors: DE YUAN XIAO, GUO QING CHEN, ROGER LEE, CHIN FU YEN, SU XING, XIAO LU HUANG, YONG SHENG YANG
  • Patent number: 8937796
    Abstract: Variable frequency motor drives and control techniques are presented in which filter capacitor faults are detected by measuring filter neutral node currents and/or voltages and detecting changes in a frequency component of the measured neutral condition and/or based on input current unbalance.
    Type: Grant
    Filed: June 26, 2012
    Date of Patent: January 20, 2015
    Assignee: Rockwell Automation Technologies, Inc.
    Inventors: Yuan Xiao, Navid Zargari, Manish Pande, Vijay Khatri
  • Publication number: 20140363314
    Abstract: A brushless motor includes a stator comprising a stator core with teeth protruding inwardly and windings wound on the teeth, and a rotor comprising a shaft, a rotor core fixed to the shaft, and a ring magnet fixed to the circumferential outer surface of the rotor core. The ring magnet includes a plurality of magnetic poles radially magnetized so that north poles and south poles are arranged alternately in the circumferential direction, boundary lines between adjacent magnetic poles being skewed by an angle ? relative to an axis of the shaft. A plurality of grooves are formed in a circumferential outer surface of the rotor core. Each groove extends from one axial end to the other axial end of the rotor core, has a circumferential width smaller than each of the magnetic poles, and is covered by the ring magnet with a void formed between the groove and the ring magnet.
    Type: Application
    Filed: August 22, 2014
    Publication date: December 11, 2014
    Inventors: Mao Xiong JIANG, Yue LI, Tao ZHANG, San Yuan XIAO, Lik Hon CHAN
  • Patent number: 8907212
    Abstract: A junction box includes a cable connecting box and a cover covering the cable connecting box. The cable connecting box includes an insulative block, a plurality of contacting foils retained in the insulative block and a plurality of diodes. Each diode connects with two neighborly contacting foils. The contacting foils are insert-molded with the insulative block. Based on thermal radiation properties of the plastic material is superior to that of the metal material, as the contacting foils transfer the heat to the insulative block, the insulative block would deliver the heat to the cable connecting box, then the heat would be delivered to the cover. Such that, the heat dissipates outside quickly from the junction box.
    Type: Grant
    Filed: July 5, 2012
    Date of Patent: December 9, 2014
    Assignee: Hon Hai Precision Industry Co., Ltd.
    Inventors: Xue-Yuan Xiao, Hong-Qiang Han, Zi-Qiang Zhu
  • Publication number: 20140353715
    Abstract: A transistor device may include a substrate that has a well portion. The transistor device may further include a source member and a drain member. The transistor device may further include a fin bar. The fin bar may be formed of a first semiconductor material, may be disposed between the source member and the drain member, and may overlap the well portion. The transistor device may further include a fin layer. The fin layer may be formed of a second semiconductor material, may be disposed between the source member and the drain member, and may contact the fin bar.
    Type: Application
    Filed: May 16, 2014
    Publication date: December 4, 2014
    Applicant: Semiconductor Manufacturing International (Shanghai) Corporation
    Inventor: De Yuan XIAO
  • Patent number: 8889510
    Abstract: A method for forming a surrounding stacked gate fin FET nonvolatile memory structure includes providing a silicon-on-insulator (SOI) substrate of a first conductivity type, patterning a fin active region on a region of the substrate, forming a tunnel oxide layer on the fin active region, and depositing a first gate electrode of a second conductivity type on the tunnel oxide layer and upper surface of the substrate. The method further includes forming a dielectric composite layer on the first gate electrode, depositing a second gate electrode on the dielectric composite layer, patterning the first and second gate electrodes to define a surrounding stacked gate area, forming a spacer layer on a sidewall of the stacked gate electrode, and forming elevated source/drain regions in the fin active region on both sides of the second gate electrode.
    Type: Grant
    Filed: July 12, 2013
    Date of Patent: November 18, 2014
    Assignees: Semiconductor Manufacturing International (Shanghai) Corporation, Semiconductor Manufacturing International (Beijing) Corporation
    Inventors: De Yuan Xiao, Lily Jiang, Gary Chen, Roger Lee
  • Patent number: 8884363
    Abstract: A system and method for integrated circuits with surrounding gate structures are disclosed. The integrated circuits system includes a transistor having a gate all around cylindrical (GAAC) nanowire channel with an interposed dielectric layer. The cylindrical nanowire channel being in a middle section of a semiconductor wire pattern connects the source and drain region positioned at the two opposite end sections of the same wire pattern.
    Type: Grant
    Filed: September 28, 2010
    Date of Patent: November 11, 2014
    Assignees: Semiconductor Manufacturing International (Shanghai) Corp., Semiconductor Manufacturing International (Beijing) Corp.
    Inventors: De Yuan Xiao, Guo Qing Chen, Roger Lee, Chin Fu Yen, Su Xing, Xiao Lu Huang, Yong Sheng Yang
  • Publication number: 20140268928
    Abstract: Multilevel inverters, power cells and bypass methods are presented in which a power cell switching circuit is selectively disconnected from the power cell output, and a bypass which is closed to connect first and second cell output terminals to selectively bypass a power stage of a multilevel inverter, with an optional AC input switch to selectively disconnect the AC input from the power cell switching circuit during bypass.
    Type: Application
    Filed: March 18, 2013
    Publication date: September 18, 2014
    Applicant: Rockwell Automation Technologies, Inc.
    Inventors: Lixiang Wei, Yuan Xiao, Haihui Lu, Douglas B. Weber
  • Publication number: 20140203243
    Abstract: Three dimensional quantum well transistors and fabrication methods are provided. A quantum well layer, a barrier layer, and a gate structure can be sequentially formed on an insulating surface of a fin part. The gate structure can be formed over the barrier layer and across the fin part. The QW layer and the barrier layer can form a hetero-junction of the transistor. A recess can be formed in the fin part on both sides of the gate structure to suspend a sidewall spacer. A source and a drain can be formed by growing an epitaxial material in the recess and the sidewall spacer formed on both sidewalls of the gate electrode can be positioned on surface of the source and the drain.
    Type: Application
    Filed: December 31, 2013
    Publication date: July 24, 2014
    Applicant: Semiconductor Manufacturing International (Shanghai) Corporation
    Inventor: DE YUAN XIAO
  • Patent number: 8779285
    Abstract: A junction box includes a cable connecting body and a cover covering the cable connecting body. The cable connecting body includes an insulative block, a plurality of connecting foils retained in the insulative block and a plurality of diodes connecting with two neighborly connecting foils. The connecting foils are insert-molded with the insulative block. The insulative block has a hook and the cable connecting body has a front wall with a depressing slot corresponding to the hook. The hook and the depressing slot engage with each other, when the insulative block is damaged, the user can remove the insulative block away from the junction box by levering the hook.
    Type: Grant
    Filed: July 5, 2012
    Date of Patent: July 15, 2014
    Assignee: Hon Hai Precision Industry Co., Ltd.
    Inventors: Xue-Yuan Xiao, Hong-Qiang Han, Zi-Qiang Zhu
  • Publication number: 20140193956
    Abstract: Fabrication methods for junctionless transistor and complementary junctionless transistor are provided. An isolation layer doped with a first-type ion is formed on a semiconductor substrate and an active layer doped with a second-type ion is formed on the isolation layer. The active layer includes a first portion between a second portion and a third portion of the active layer. Portions of the isolation layer under the second and third portions of the active layer are removed to suspend the second and third portions of the active layer. A gate structure is formed on the first portion of the active layer. A source and a drain are formed by doping the second portion and the third portion of the active layer with the second-type ion on both sides of the gate structure. The source and the drain have a same doping type as the first portion of the active layer.
    Type: Application
    Filed: December 30, 2013
    Publication date: July 10, 2014
    Applicant: Semiconductor Manufacturing International (Shanghai) Corporation
    Inventor: DE YUAN XIAO
  • Patent number: 8748743
    Abstract: A junction box includes a cable connecting box including an insulative box and a wire connecting module assembled to the insulative box. The insulative box has a receiving cavity, a bottom wall under the receiving cavity, a plurality of walls surrounding around the receiving cavity, at least a supporting portion located in the walls, a locking slot defined between the supporting portion and one of the walls, and a resilient locking portion received in the locking slot. A cover covers the cable connecting box and comprises a latching portion protruding outwardly from a side of the cover to lock with the resilient locking portion in the locking slot. In this arrangement, the junction box is convenient for users service.
    Type: Grant
    Filed: July 5, 2012
    Date of Patent: June 10, 2014
    Assignee: Hon Hai Precision Industry Co., Ltd.
    Inventors: Xue-Yuan Xiao, Hong-Qiang Han, Zi-Qiang Zhu
  • Publication number: 20140132295
    Abstract: The present techniques include methods and systems for detecting a failure in a capacitor bank of an electrical drive system. Embodiments include using discharge resistors to discharge capacitors in the capacitor bank, forming a neutral node of the capacitor bank. In different capacitor configurations, the neutral node is measured, and the voltage is analyzed to determine whether a capacitor bank unbalance has occurred. In some embodiments, the node is a neutral-to-neutral node between the discharged side of the discharge resistors and a neutral side of the capacitor bank, or between the discharged side of the discharge resistors and a discharged side of a second set of discharge resistors. In some embodiments, the node is a neutral-to-ground node between the discharged side of the discharge resistors and a ground potential.
    Type: Application
    Filed: January 20, 2014
    Publication date: May 15, 2014
    Applicant: ROCKWELL AUTOMATION TECHNOLOGIES, INC.
    Inventors: Yuan Xiao, Lixiang Wei, Doyle F. Busse
  • Patent number: 8723034
    Abstract: A junction box includes a cable connecting box, a cover covering the cable connecting box and an o-ring sealing between the cover and the cable connecting box. The cable connecting box includes an insulative block, a plurality of contacting foils retained in the insulative block, a plurality of diodes connecting with two neighborly contacting foils and four walls surrounding around the insulative block. The cover defines a sealing slot for receiving the o-ring. The sealing slot has a bump at a place of the molding joint of the cover to enlarge a deformation of the o-ring for improving a waterproof effect of the junction box.
    Type: Grant
    Filed: July 5, 2012
    Date of Patent: May 13, 2014
    Assignee: Hon Hai Precision Industry Co., Ltd.
    Inventors: Xue-Yuan Xiao, Hong-Qiang Han, Zi-Qiang Zhu
  • Publication number: 20140076603
    Abstract: A screw retaining mechanism includes a hollow stud and a nut is matched with the hollow stud. The hollow stud has a plurality of elastic plates extending from a free end thereof and along a peripheral wall thereof An opening is located between two adjacent elastic plates. An inner wall of the nut has a plurality of tubers protruding in the axial direction to match into the opening. The elastic plate defines a first side face and a second side face opposite to the first side face. Said first side face is used to guide the tubers into the opening and the second side face prevent the tuber fall off from the stud.
    Type: Application
    Filed: September 18, 2013
    Publication date: March 20, 2014
    Applicant: HON HAI PRECISION INDUSTRY CO., LTD.
    Inventors: XUE-YUAN XIAO, ZHANG-LAN XUE, ZI-QIANG ZHU
  • Patent number: 8653931
    Abstract: Power conversion systems and integrated multi-phase chokes providing high common mode to differential mode choke inductance ratios with circular and triangular shapes for concurrent differential filtering and common-mode voltage blocking in motor drives and other power conversion applications.
    Type: Grant
    Filed: October 27, 2010
    Date of Patent: February 18, 2014
    Assignee: Rockwell Automation Technologies, Inc.
    Inventors: David Dewei Xu, Ning Zhu, Yuan Xiao, Bin Wu
  • Publication number: 20140042817
    Abstract: Bypassing methods and apparatus are presented along with power cells and sub cells for multilevel inverters in which DC current flow into a DC link capacitance is interrupted and a bypass switch is closed across a power cell or sub cell output to selectively bypass a power stage of a multilevel inverter.
    Type: Application
    Filed: August 13, 2012
    Publication date: February 13, 2014
    Applicant: ROCKWELL AUTOMATION TECHNOLOGIES, INC.
    Inventors: Navid Zargari, Yuan Xiao, Lixiang Wei
  • Patent number: 8643383
    Abstract: The present techniques include methods and systems for detecting a failure in a capacitor bank of an electrical drive system. Embodiments include using discharge resistors to discharge capacitors in the capacitor bank, forming a neutral node of the capacitor bank. In different capacitor configurations, the neutral node is measured, and the voltage is analyzed to determine whether a capacitor bank unbalance has occurred. In some embodiments, the node is a neutral-to-neutral node between the discharged side of the discharge resistors and a neutral side of the capacitor bank, or between the discharged side of the discharge resistors and a discharged side of a second set of discharge resistors. In some embodiments, the node is a neutral-to-ground node between the discharged side of the discharge resistors and a ground potential.
    Type: Grant
    Filed: January 28, 2011
    Date of Patent: February 4, 2014
    Assignee: Rockwell Automation Technologies, Inc.
    Inventors: Yuan Xiao, Lixiang Wei, Doyle F. Busse