Patents by Inventor Yuan Yang

Yuan Yang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 12224661
    Abstract: Controller and method for a quasi-resonant switching power supply. For example, a controller for a quasi-resonant switching power supply includes: a valley detector configured to receive a voltage signal, detect one or more voltage valleys of the voltage signal in magnitude, and generate a detection signal representing the detected one or more voltage valleys; a valley-locking controller configured to receive one or more signals, generate a mode control signal that indicates a selected valley-locking mode based at least in part on the one or more signals, select from the detected one or more voltage valleys, one or more valleys that correspond to the selected valley-locking mode, and generate a valley control signal indicating the one or more selected valleys; and a gate driver configured to generate a drive signal based on at least information associated with the valley control signal.
    Type: Grant
    Filed: October 31, 2023
    Date of Patent: February 11, 2025
    Assignee: On-Bright Electronics (Shanghai) Co., Ltd.
    Inventors: Penglin Yang, Yuan Lin
  • Publication number: 20250048781
    Abstract: A modulator heater structure may include a plurality of regions having different thicknesses. For example, a heater ring of the modulator heater structure may have a first thickness. A heater pad of the modulator heater structure, that is configured to provide an electrical current to the heater ring, may have a second thickness that is greater than the first thickness. The lesser thickness of the heater ring of the modulator heater structure provides high electrical resistance in the heater ring, which enables the heater ring to quickly and efficiently generate heat. The greater thickness of the heater pad provides low electrical resistance in the second region, which enables the electrical current to be efficiently provided through the heater pad to the heater ring with reduced heat dissipation in the hear pad due to the lower electrical current dissipation in the heater pad.
    Type: Application
    Filed: August 4, 2023
    Publication date: February 6, 2025
    Inventors: Wen-Shun LO, Sheng Kai YEH, Jing-Hwang YANG, Chi-Yuan SHIH, Shih-Fen HUANG, YingKit Felix TSUI
  • Patent number: 12219747
    Abstract: SRAM designs based on GAA transistors are disclosed that provide flexibility for increasing channel widths of transistors at scaled IC technology nodes and relax limits on SRAM performance optimization imposed by FinFET-based SRAMs. GAA-based SRAM cells described have active region layouts with active regions shared by pull-down GAA transistors and pass-gate GAA transistors. A width of shared active regions that correspond with the pull-down GAA transistors are enlarged with respect to widths of the shared active regions that correspond with the pass-gate GAA transistors. A ratio of the widths is tuned to obtain ratios of pull-down transistor effective channel width to pass-gate effective channel width greater than 1, increase an on-current of pull-down GAA transistors relative to an on-current of pass-gate GAA transistors, decrease a threshold voltage of pull-down GAA transistors relative to a threshold voltage of pass-gate GAA transistors, and/or increases a ? ratio of an SRAM cell.
    Type: Grant
    Filed: August 12, 2021
    Date of Patent: February 4, 2025
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Chia-Hao Pao, Chih-Chuan Yang, Shih-Hao Lin, Chih-Hsuan Chen, Kian-Long Lim, Chao-Yuan Chang, Feng-Ming Chang, Lien Jung Hung, Ping-Wei Wang
  • Patent number: 12218186
    Abstract: A device structure according to the present disclosure includes a metal-insulator-metal (MIM) stack that includes a plurality of conductor plate layers interleaved by a plurality of insulator layers. The MIM stack includes a first region and a second region and the first region and the second region overlaps in a third region. The MIM stack further includes a first via passing through the first region and electrically coupled to a first subset of the plurality of conductor plate layers, a second via passing through the second region and electrically coupled to a second subset of the plurality of conductor plate layers, and a ground via passing through the third region and electrically coupled to a third subset of the plurality of conductor plate layers.
    Type: Grant
    Filed: February 7, 2022
    Date of Patent: February 4, 2025
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Wen-Chiung Tu, Hsiang-Ku Shen, Yuan-Yang Hsiao, Tsung-Chieh Hsiao, Chen-Chiu Huang, Dian-Hau Chen
  • Patent number: 12218130
    Abstract: Methods of cutting gate structures, and structures formed, are described. In an embodiment, a structure includes first and second gate structures over an active area, and a gate cut-fill structure. The first and second gate structures extend parallel. The active area includes a source/drain region disposed laterally between the first and second gate structures. The gate cut-fill structure has first and second primary portions and an intermediate portion. The first and second primary portions abut the first and second gate structures, respectively. The intermediate portion extends laterally between the first and second primary portions. First and second widths of the first and second primary portions along longitudinal midlines of the first and second gate structures, respectively, are each greater than a third width of the intermediate portion midway between the first and second gate structures and parallel to the longitudinal midline of the first gate structure.
    Type: Grant
    Filed: December 1, 2023
    Date of Patent: February 4, 2025
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Chih-Chang Hung, Chia-Jen Chen, Ming-Ching Chang, Shu-Yuan Ku, Yi-Hsuan Hsiao, I-Wei Yang
  • Publication number: 20250038072
    Abstract: A semiconductor die includes a substrate, a semiconductor device, a back-end-of-line (BEOL) structure, and a heat dissipation structure. The substrate includes a device region and a non-device region. The BEOL structure includes a plurality of metallization layers. Each of the metallization layers includes a dielectric layer, interconnect features, and metal patterns. The interconnect features is in the dielectric layer and over the device region of the substrate, in which the interconnect features are electrically connected with the semiconductor device. The metal patterns are in the dielectric layer and over the non-device region of the substrate, in which the metal patterns are electrically isolated from the semiconductor device. The heat dissipation structure is over the non-device region of the substrate and extending through at least two of the metallization layers, in which the heat dissipation structure is in contact with the metal patterns of one of the metallization layers.
    Type: Application
    Filed: July 27, 2023
    Publication date: January 30, 2025
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Hsin-Yuan LEE, Chih-Kai YANG, Ken-Hsien HSIEH, Ya Hui CHANG
  • Publication number: 20250040294
    Abstract: A semiconductor device is provided, which includes an active structure, a first semiconductor layer, a second semiconductor layer, an insulating layer, and a conductive layer. The active region has two sides and includes an active region. The first semiconductor layer and the second semiconductor layer respectively located on the two sides of the active structure. The insulating layer covers a portion of the first semiconductor layer. The conductive layer covers the insulating layer and physically contacts the first semiconductor layer. The second semiconductor layer includes a first dopant and the first semiconductor layer includes a second dopant different from the first dopant. The first semiconductor layer includes a quaternary III-V semiconductor material, and the active region includes a quaternary semiconductor material, and the semiconductor device emits a radiation having a peak wavelength between 800 nm and 2000 nm.
    Type: Application
    Filed: September 25, 2024
    Publication date: January 30, 2025
    Inventors: Meng-Yang CHEN, Yuan-Ting LIN
  • Patent number: 12208365
    Abstract: A gene chip includes a chip carrier, a plurality of DNA nanoballs assembled on the chip carrier, and a polymer film formed on the chip carrier and wrapping the DNA nanoballs. The polymer film includes at least one of a film of a positively charged polymer, a film of a positively charged polymer which is modified, a film of a zwitterionic polymer, and a composite polymer film. The composite polymer film is formed by a layer-by-layer self-assembly process of a positively charged polymer and a negatively charged polymer. The gene chip has good sequencing quality and different functions can be achieved by coating with different polymers, such as the chip surface rapidly drying out and surface non-specific adsorption. A method of preparing a gene chip is further disclosed.
    Type: Grant
    Filed: August 15, 2018
    Date of Patent: January 28, 2025
    Assignee: BGI SHENZHEN
    Inventors: Zhao-Hui Wang, Hui Wang, Cheng-Mei Xing, Han-Dong Li, Wen-Wei Zhang, Jay Willis Shafto, Mei-Hua Gong, Jin Yang, Yin-Ling Luo, Zhen-Hua Zhang, Yuan Li, Xue-Qin Jiang
  • Patent number: 12210146
    Abstract: A structured material is provided that includes a substrate and a porous structured polymer layer disposed thereon. The porous structured polymer layer includes a plurality of voids, and has a high hemispherical reflectance a high a hemispherical thermal emittance. The structured material is thus particularly advantageous for cool-roof coatings, enabling surfaces coated by the material to stay cool, even under strong sunlight. The material can be produced via structuring of polymers in a mixture including a solvent and a non-solvent. Sequential evaporation of the solvent and the non-solvent provide a polymer layer with the plurality of voids.
    Type: Grant
    Filed: August 8, 2023
    Date of Patent: January 28, 2025
    Assignee: THE TRUSTEES OF COLUMBIA UNIVERSITY IN THE CITY OF NEW YORK
    Inventors: Jyotirmoy Mandal, Yuan Yang, Nanfang Yu
  • Patent number: 12211793
    Abstract: The present disclosure, in some embodiments, relates to an integrated circuit. The integrated circuit includes first and second source/drain regions on or within a substrate. A first gate is arranged over the substrate between the first source/drain region and the second source/drain region. A first middle-end-of-the-line (MEOL) structure is arranged over the second source/drain region and a second MEOL structure is arranged over a third source/drain region. A conductive structure contacts the first MEOL structure and the second MEOL structure. A second gate is separated from the first gate by the second source/drain region. The conductive structure vertically and physically contacts a top surface of the second gate that is coupled to outermost sidewalls of the second gate. A plurality of conductive contacts are configured to electrically couple an interconnect wire and the first MEOL structure along one or more conductive paths extending through the conductive structure.
    Type: Grant
    Filed: July 18, 2022
    Date of Patent: January 28, 2025
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Ni-Wan Fan, Ting-Wei Chiang, Cheng-I Huang, Jung-Chan Yang, Hsiang-Jen Tseng, Lipen Yuan, Chi-Yu Lu
  • Publication number: 20250028424
    Abstract: This disclosure provides an icon splicing method and related device. In this method, a terminal device may display a first icon, and display a second icon in response to an operation of triggering to splice the first icon; display, in response to an operation of selecting the second icon and the first icon for splicing, options of a plurality of functions corresponding to the second icon; and display, in response to an operation of selecting an option of a second function, a spliced icon of the first icon and the second icon. The second function includes one or more of the plurality of functions corresponding to the second icon. The spliced icon has a function of supporting linkage between a first function and the second function. The first function includes one or more of a plurality of functions corresponding to the first icon.
    Type: Application
    Filed: December 9, 2022
    Publication date: January 23, 2025
    Applicant: HUAWEI TECHNOLOGIES CO., LTD.
    Inventors: Li Zhang, Wanyi Yang, Feng Chen, Yuan Cao
  • Publication number: 20250026813
    Abstract: The present invention relates to antibodies that are specific for SARS-CoV-2. The present invention also provides methods of treatment, uses, pharmaceutical compositions and kits comprising the antibodies.
    Type: Application
    Filed: October 27, 2021
    Publication date: January 23, 2025
    Inventors: Paul Kellam, Anne Palser, Volker Germaschewski, Simon James Watson, Benjamin David Grimshaw, Spela Binter, Jaroslaw Michal Szary, Margot Billaud, Robert Rowlands, Aishwarya Krishna, Huan-Chun Lin, Cheng-Yuan Yang, Li-Ying Liou
  • Publication number: 20240406116
    Abstract: A virtual circuit in a network device reformats one or more incoming data streams at a non-predetermined data rate into an outgoing data stream at a predetermined data rate, thereby allowing multiple data streams with non-predetermined data rates that are less than the predetermined data rate to be combined and output from a single network port.
    Type: Application
    Filed: August 13, 2024
    Publication date: December 5, 2024
    Inventors: Ming LI, Yuan Yang JIA
  • Patent number: 12155561
    Abstract: A method for managing network connections includes steps of: in response to receipt of a request for establishing a new network connection, storing in a connection-tracking (Conntrack) table an entry of tracked connection data that is related to the new network connection to be established, and updating a current tracked-connection count by adding one thereto; determining a priority level of the new network connection according to a data packet transmitted through the new network connection; and determining whether to output data packets that are received through the new network connection based at least on the current tracked-connection count and the priority level of the new network connection.
    Type: Grant
    Filed: January 21, 2022
    Date of Patent: November 26, 2024
    Assignee: GT BOOSTER INC.
    Inventors: Shun-Yuan Yang, Chiao Min Hu, Wei-Teng Tai
  • Publication number: 20240387617
    Abstract: A method of manufacturing a semiconductor device includes forming a first conductive layer over a first insulating layer and forming a first dielectric layer over the first conductive layer. A second conductive layer is formed over a first portion of the first dielectric layer. A second dielectric layer is formed over the second conductive layer. A third conductive layer is formed over the second dielectric layer and the second portion of the first dielectric layer. A third dielectric layer is formed over the third conductive layer. A first conductive contact is formed contacting the first conductive layer. A second conductive contact is formed contacting the third conductive layer. The second conductive layer is an electrically floating layer.
    Type: Application
    Filed: July 29, 2024
    Publication date: November 21, 2024
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Tsung-Chieh HSIAO, Hsiang-Ku SHEN, Yuan-Yang HSIAO, Wen-Chiung TU, Chen-Chiu HUANG, Dian-Hau CHEN
  • Publication number: 20240383100
    Abstract: A method includes depositing a slurry onto a polishing pad of a chemical mechanical polishing (CMP) station. A workpiece is polished and polishing by-products and slurry are removed from the polishing pad by a vacuum head. A CMP apparatus includes a polishing pad configured to rotate during a CMP process. The apparatus also includes a slurry dispenser configured to deposit a slurry onto a polishing surface of the polishing pad. The apparatus further includes a momentum vacuum assembly including a slotted opening facing the polishing surface of the polishing pad. The apparatus also includes a first suction line coupled to an upper portion of the momentum vacuum assembly and leading to a first vacuum source, the first suction line configured to transport polishing products which have been removed from the polishing pad through the slotted opening.
    Type: Application
    Filed: July 29, 2024
    Publication date: November 21, 2024
    Inventors: Yu-Chen Wei, Chih-Yuan Yang, Shih-Ho Lin, Jen Chieh Lai, Szu-Cheng Wang, Chun-Jui Chu
  • Publication number: 20240379734
    Abstract: A semiconductor device includes a metal-insulator-metal (MIM) capacitor. The MIM capacitor includes: electrodes including one or more first electrodes and one or more second electrodes; and one or more insulating layers disposed between adjacent electrodes. The MIM capacitor is disposed in an interlayer dielectric (ILD) layer disposed over a substrate. The one or more first electrodes are connected to a side wall of a first via electrode disposed in the ILD layer, and the one or more second electrodes are connected to a side wall of a second via electrode disposed in the ILD layer. In one or more of the foregoing or following embodiments, the one or more insulating layers include a high-k dielectric material.
    Type: Application
    Filed: July 24, 2024
    Publication date: November 14, 2024
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Tsung-Chieh HSIAO, Hsiang-Ku SHEN, Yuan-Yang HSIAO, Ying-Yao LAI, Dian-Hau CHEN
  • Publication number: 20240379529
    Abstract: A metal-insulator-metal (MIM) structure and methods of forming the same for reducing the accumulation of external stress at the corners of the conductor layers are disclosed herein. An exemplary device includes a substrate that includes an active semiconductor device. A stack of dielectric layers is disposed over the substrate. A lower contact is disposed over the stack of dielectric layers. A passivation layer is disposed over the lower contact. A MIM structure is disposed over the passivation layer, the MIM structure including a first conductor layer, a second conductor layer disposed over the first conductor layer, and a third conductor layer disposed over the second conductor layer. A first insulator layer is disposed between the first conductor layer and the second conductor layer. A second insulator layer is disposed between the second conductor layer and the third conductor layer. One or more corners of the third conductor layer are rounded.
    Type: Application
    Filed: July 22, 2024
    Publication date: November 14, 2024
    Inventors: Yuan-Yang Hsiao, Hsiang-Ku Shen, Dian-Hau Chen, Hsiao Ching-Wen, Yao-Chun Chuang
  • Publication number: 20240379593
    Abstract: Methods and semiconductor structures are provided. A semiconductor structure according to the present disclosure includes a plurality of transistors, an interconnect structure electrically coupled to the plurality of transistors, a metal feature disposed over the interconnect structure and electrically isolated from the plurality of transistors, an insulation layer disposed over the metal feature, and a first redistribution feature and a second redistribution feature disposed over the insulation layer. A space between the first redistribution feature and the second redistribution feature is disposed directly over at least a portion of the metal feature.
    Type: Application
    Filed: July 12, 2024
    Publication date: November 14, 2024
    Inventors: Kuo-An Liu, Wen-Chiung Tu, Yuan-Yang Hsiao, Kai Tak Lam, Chen-Chiu Huang, Zhiqiang Wu, Dian-Hau Chen
  • Publication number: 20240379531
    Abstract: A device structure according to the present disclosure includes a passivation layer, a first conductor plate layer disposed on the passivation layer, a second conductor plate layer disposed over the first conductor layer, a third conductor plate layer disposed over the second conductor layer, and a fourth conductor plate layer disposed over the third conductor layer. The second conductor plate layer encloses the first conductor plate layer and the fourth conductor plate layer encloses the third conductor plate layer. The device structure, when used in a back-end-of-line passive device, reduces leakage and breakdown due to corner discharge effect.
    Type: Application
    Filed: July 25, 2024
    Publication date: November 14, 2024
    Inventors: Tsung-Chieh Hsiao, Hsiang-Ku Shen, Yuan-Yang Hsiao, Chen-Chiu Huang, Dian-Hau Chen