Abstract: A controller includes a link interface that is to couple to a first link to communicate bi-directional data and a second link to transmit unidirectional error-detection information. An encoder is to dynamically add first error-detection information to at least a portion of write data. A transmitter, coupled to the link interface, is to transmit the write data. A delay element is coupled to an output from the encoder. A receiver, coupled to the link interface, is to receive second error-detection information corresponding to at least the portion of the write data. Error-detection logic is coupled to an output from the delay element and an output from the receiver. The error-detection logic is to determine errors in at least the portion of the write data by comparing the first error-detection information and the second error-detection information, and, if an error is detected, is to assert an error condition.

Abstract: The present invention provides an I2C interface system for high-speed long-distance I2C transmission, which includes an I2C interface module and at least one functional module; the I2C interface module is connected with an I2C master controller through an I2C clock line and an I2C data line; the functional module is connected with the I2C interface module. The present invention is suitable for application scenes with a long transmission distance or a large signal interference, and the I2C system used for long-distance transmission has a fast acknowledge speed and a fast transmission speed.

Abstract: The timing of the synchronous interface is controlled by a clock signal driven by a controller. The clock is toggled in order to send a command to a memory device via the interface. If there are no additional commands to be sent via the interface, the controller suspends the clock signal. When the memory device is ready, the memory device drives a signal back to the controller. The timing of this signal is not dependent upon the clock signal. Receipt of this signal by the controller indicates that the memory device is ready and the clock signal should be resumed so that a status of the command can be returned via the interface, or another command issued via the interface.

Abstract: The present invention provides a multi-rate bidirectional transmission system. A sending device and a receiving device transmit data in a bidirectional way through a cable. The multi-rate bidirectional transmission system communicates with a reverse configuration packet by sending a forward configuration packet at a preset rate in a time-division manner, selects a serial rate jointly supported by the sending device and the receiving device, and selects a training sequence length. Then, the sending device and the receiving device perform equalization training at the selected serial rate with the selected training sequence length, thus avoiding searching the serial rate and presetting the training sequence length in the worst case, thus simplifying the design and improving the link training speed.

Abstract: A video transmission system includes a first transmission terminal, a second transmission terminal and a transmission channel. The first transmission terminal includes a transmission memory, and stores a retransmittable data packet into the transmission memory and sends the retransmittable data packet to the second transmission terminal. The second transmission terminal judges the abnormal state of the received retransmittable data packet, generates and sends retransmission control information according to a judgment result. The first transmission terminal retransmits the retransmittable data packet to the second transmission terminal according to the retransmission control information. The first transmission terminal sends a real-time data packet to the second transmission terminal. The real-time data packet is used to transmit video timing control signals.

Abstract: A 9B/10B encoding method is used for encoding a 9-bit source sequence set, including first type, second type and third type of 9-bit source sequence sets, into a 10-bit target sequence set. The first type of 9-bit source sequence set only includes 9-bit source sequences with difference values of 1 and ?1. After inserting 1-bit data “0” or “1” in each sequence, each sequence is encoded as a 10-bit target balanced sequence; the second type of 9-bit source sequence set alternatively includes only 9-bit source sequences with difference values of 3 or ?3. After inserting 1-bit data “0” or “1” into each sequence, each sequence is encoded into a pair of 10-bit target unbalanced sequences with a difference value of ±2; each sequence in the third type of 9-bit source sequence set is encoded as a pair of 10-bit target unbalanced sequences that are opposite numbers for each other.

Abstract: The timing of the synchronous interface is controlled by a clock signal driven by a controller. The clock is toggled in order to send a command to a memory device via the interface. If there are no additional commands to be sent via the interface, the controller suspends the clock signal. When the memory device is ready, the memory device drives a signal back to the controller. The timing of this signal is not dependent upon the clock signal. Receipt of this signal by the controller indicates that the memory device is ready and the clock signal should be resumed so that a status of the command can be returned via the interface, or another command issued via the interface.

Abstract: A controller includes a link interface that is to couple to a first link to communicate bi-directional data and a second link to transmit unidirectional error-detection information. An encoder is to dynamically add first error-detection information to at least a portion of write data. A transmitter, coupled to the link interface, is to transmit the write data. A delay element is coupled to an output from the encoder. A receiver, coupled to the link interface, is to receive second error-detection information corresponding to at least the portion of the write data. Error-detection logic is coupled to an output from the delay element and an output from the receiver. The error-detection logic is to determine errors in at least the portion of the write data by comparing the first error-detection information and the second error-detection information, and, if an error is detected, is to assert an error condition.

Abstract: A physical layer retransmission control method is used for retransmission control of a transmission system. The transmission system includes a first transmission terminal, a second transmission terminal and a transmission channel. The first transmission terminal sends downlink data packets to the second transmission terminal through the transmission channel. The second transmission terminal sends retransmission control information to the first transmission terminal through the transmission channel. Each downlink data packet includes a sequence number and an abnormal state field. The sequence numbers in the consecutive downlink data packets are arranged in the order of transmission. The abnormal state field indicates the abnormal state of the data of the first transmission terminal.

Abstract: The timing of the synchronous interface is controlled by a clock signal driven by a controller. The clock is toggled in order to send a command to a memory device via the interface. If there are no additional commands to be sent via the interface, the controller suspends the clock signal. When the memory device is ready, the memory device drives a signal back to the controller. The timing of this signal is not dependent upon the clock signal. Receipt of this signal by the controller indicates that the memory device is ready and the clock signal should be resumed so that a status of the command can be returned via the interface, or another command issued via the interface.

Abstract: A memory controller includes an interface to receive a data strobe signal and corresponding read data. The data strobe signal and the read data correspond to a read command issued by the memory controller, and the read data is received in accordance with the data strobe signal and an enable signal. A circuit in the memory controller is to dynamically adjust a timing offset between the enable signal and the data strobe signal, and control logic is to issue a supplemental read command in accordance with a determination that a time interval since a last read command issued by the memory controller exceeds a predetermined value.

Abstract: The present invention provides a multi-rate bidirectional transmission system. A sending device and a receiving device transmit data in a bidirectional way through a cable. The multi-rate bidirectional transmission system communicates with a reverse configuration packet by sending a forward configuration packet at a preset rate in a time-division manner, selects a serial rate jointly supported by the sending device and the receiving device, and selects a training sequence length. Then, the sending device and the receiving device perform equalization training at the selected serial rate with the selected training sequence length, thus avoiding searching the serial rate and presetting the training sequence length in the worst case, thus simplifying the design and improving the link training speed.

Abstract: The timing of the synchronous interface is controlled by a clock signal driven by a controller. The clock is toggled in order to send a command to a memory device via the interface. If there are no additional commands to be sent via the interface, the controller suspends the clock signal. When the memory device is ready, the memory device drives a signal back to the controller. The timing of this signal is not dependent upon the clock signal. Receipt of this signal by the controller indicates that the memory device is ready and the clock signal should be resumed so that a status of the command can be returned via the interface, or another command issued via the interface.

Abstract: A controller includes a link interface that is to couple to a first link to communicate bi-directional data and a second link to transmit unidirectional error-detection information. An encoder is to dynamically add first error-detection information to at least a portion of write data. A transmitter, coupled to the link interface, is to transmit the write data. A delay element is coupled to an output from the encoder. A receiver, coupled to the link interface, is to receive second error-detection information corresponding to at least the portion of the write data. Error-detection logic is coupled to an output from the delay element and an output from the receiver. The error-detection logic is to determine errors in at least the portion of the write data by comparing the first error-detection information and the second error-detection information, and, if an error is detected, is to assert an error condition.

Abstract: A controller includes a link interface that is to couple to a first link to communicate bi-directional data and a second link to transmit unidirectional error-detection information. An encoder is to dynamically add first error-detection information to at least a portion of write data. A transmitter, coupled to the link interface, is to transmit the write data. A delay element is coupled to an output from the encoder. A receiver, coupled to the link interface, is to receive second error-detection information corresponding to at least the portion of the write data. Error-detection logic is coupled to an output from the delay element and an output from the receiver. The error-detection logic is to determine errors in at least the portion of the write data by comparing the first error-detection information and the second error-detection information, and, if an error is detected, is to assert an error condition.

Abstract: The timing of the synchronous interface is controlled by a clock signal driven by a controller. The clock is toggled in order to send a command to a memory device via the interface. If there are no additional commands to be sent via the interface, the controller suspends the clock signal. When the memory device is ready, the memory device drives a signal back to the controller. The timing of this signal is not dependent upon the clock signal. Receipt of this signal by the controller indicates that the memory device is ready and the clock signal should be resumed so that a status of the command can be returned via the interface, or another command issued via the interface.

Abstract: A controller includes a link interface that is to couple to a first link to communicate bi-directional data and a second link to transmit unidirectional error-detection information. An encoder is to dynamically add first error-detection information to at least a portion of write data. A transmitter, coupled to the link interface, is to transmit the write data. A delay element is coupled to an output from the encoder. A receiver, coupled to the link interface, is to receive second error-detection information corresponding to at least the portion of the write data. Error-detection logic is coupled to an output from the delay element and an output from the receiver. The error-detection logic is to determine errors in at least the portion of the write data by comparing the first error-detection information and the second error-detection information, and, if an error is detected, is to assert an error condition.

Abstract: The present invention discloses a dual-mode USB device, which includes a USB2.0 controller, a dual-mode USB2.0 interface module and a USB interface. The dual-mode USB device alternatively works in a USB2.0 standard mode or a USB2.0 extended mode. In the USB2.0 standard mode, DP and DM signals of the USB2.0 interface are connected to a remote USB interface by DC coupling, and is compatible with remote devices using USB2.0 standard signals and protocols; in the USB2.0 extended mode, DP and DM signals of the USB2.0 interface are connected to the remote USB interface by AC coupling, which is compatible with remote devices supporting the USB2.0 extended mode.

Abstract: A memory controller includes an interface to receive a data strobe signal and corresponding read data. The data strobe signal and the read data correspond to a read command issued by the memory controller, and the read data is received in accordance with the data strobe signal and an enable signal. A circuit in the memory controller is to dynamically adjust a timing offset between the enable signal and the data strobe signal, and control logic is to issue a supplemental read command in accordance with a determination that a time interval since a last read command issued by the memory controller exceeds a predetermined value.

Abstract: The timing of the synchronous interface is controlled by a clock signal driven by a controller. The clock is toggled in order to send a command to a memory device via the interface. If there are no additional commands to be sent via the interface, the controller suspends the clock signal. When the memory device is ready, the memory device drives a signal back to the controller. The timing of this signal is not dependent upon the clock signal. Receipt of this signal by the controller indicates that the memory device is ready and the clock signal should be resumed so that a status of the command can be returned via the interface, or another command issued via the interface.