Patents by Inventor Yuanlong Wang
Yuanlong Wang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 9658958Abstract: A control apparatus with multiple flash memory card channels includes a host side port unit, an instruction data processing unit, and flash memory card port units. The host side port unit exchanges a host side instruction and host side read/write data with a high-speed serial communication protocol host side. The flash memory card port units respectively exchange flash memory card instructions and flash memory card read/write data with a plurality of flash memory cards. An instruction from the high-speed serial communication protocol host side is divided into multiple sub-instructions to be respectively transmitted to the flash memory card port units and exchange of instruction and data with a plurality of flash memory cards is carried out in a coincident period of time so as to achieve the purposes of expanding access capacity and increasing access speed, reducing the operation cost of products, and enhancing flexibility of use of flash memory cards.Type: GrantFiled: July 26, 2013Date of Patent: May 23, 2017Assignee: NOREL SYSTEMS LIMITEDInventors: Miao Chen, Yuanlong Wang
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Patent number: 9477547Abstract: A controller includes a link interface that is to couple to a first link to communicate bi-directional data and a second link to transmit unidirectional error-detection information. An encoder is to dynamically add first error-detection information to at least a portion of write data. A transmitter, coupled to the link interface, is to transmit the write data. A delay element is coupled to an output from the encoder. A receiver, coupled to the link interface, is to receive second error-detection information corresponding to at least the portion of the write data. Error-detection logic is coupled to an output from the delay element and an output from the receiver. The error-detection logic is to determine errors in at least the portion of the write data by comparing the first error-detection information and the second error-detection information, and, if an error is detected, is to assert an error condition.Type: GrantFiled: September 14, 2015Date of Patent: October 25, 2016Assignee: Rambus Inc.Inventors: Yuanlong Wang, Frederick A. Ware
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Publication number: 20160239467Abstract: A method and system for selecting an encoding format used for reading a target document are provided. The method comprises reading a reference document with at least one reference encoding format and determining all or some disorder code patterns obtained when reading the reference document with the reference encoding format; reading the target document with one encoding format each time; for each encoding format, comparing data generated when reading the target document with this encoding format and the determined disorder code patterns to determine disorder codes generated when reading the target document with this encoding format; counting disorder codes generated when reading the target document with each encoding format, and making a comparison to determine the encoding format used for reading the target document.Type: ApplicationFiled: December 6, 2013Publication date: August 18, 2016Inventors: Mao YE, Wei WAN, Lifeng JIN, Yuanlong WANG
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Publication number: 20160232953Abstract: A memory controller includes an interface to receive a data strobe signal and corresponding read data. The data strobe signal and the read data correspond to a read command issued by the memory controller, and the read data is received in accordance with the data strobe signal and an enable signal. A circuit in the memory controller is to dynamically adjust a timing offset between the enable signal and the data strobe signal, and control logic is to issue a supplemental read command in accordance with a determination that a time interval since a last read command issued by the memory controller exceeds a predetermined value.Type: ApplicationFiled: February 5, 2016Publication date: August 11, 2016Inventors: Bret Stott, Frederick A. Ware, Ian P. Shaeffer, Yuanlong Wang
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Publication number: 20160224564Abstract: A method and system for key knowledge point recommendation are provided, the method comprising calculating knowledge point relationship strengths of knowledge points in a set of knowledge points; calculating weights for knowledge points according to the knowledge point relationship strengths of knowledge points in the set of knowledge points, and storing the knowledge points and weights correspondingly; determining key knowledge points according to the weights of the knowledge points and recommending the key knowledge points to a user.Type: ApplicationFiled: December 6, 2013Publication date: August 4, 2016Inventors: Mao YE, Jianbo XU, Zhi TANG, Lifeng JIN, Yuanlong WANG
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Publication number: 20160217376Abstract: In the method and system for knowledge extraction of this invention, knowledge extraction is realized through acquiring an initial sentence group including one or more sentences, and then comparing the length of the initial sentence group with an expected length to determine the initial sentence group to be expanded according to the comparison result. Since the sentence groups are formed by consecutive sentences, it may be guaranteed that the sentence groups themselves have good coherence in logic, so that the final sentence groups obtained through expanding the initial sentence groups have good coherence in logic correspondingly. Thus, this invention may override the drawback of lacking logical coherence in extracted knowledge information in the prior art.Type: ApplicationFiled: December 6, 2013Publication date: July 28, 2016Inventors: Mao YE, Lifeng JIN, Chao LEI, Yuanlong WANG, Zhi TANG, Jianbo XU
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Patent number: 9298543Abstract: A controller includes a link interface that is to couple to a first link to communicate bi-directional data and a second link to transmit unidirectional error-detection information. An encoder is to dynamically add first error-detection information to at least a portion of write data. A transmitter, coupled to the link interface, is to transmit the write data. A delay element is coupled to an output from the encoder. A receiver, coupled to the link interface, is to receive second error-detection information corresponding to at least the portion of the write data. Error-detection logic is coupled to an output from the delay element and an output from the receiver. The error-detection logic is to determine errors in at least the portion of the write data by comparing the first error-detection information and the second error-detection information, and, if an error is detected, is to assert an error condition.Type: GrantFiled: July 22, 2015Date of Patent: March 29, 2016Assignee: Rambus Inc.Inventors: Yuanlong Wang, Frederick A. Ware
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Patent number: 9262269Abstract: A controller includes a link interface that is to couple to a first link to communicate bi-directional data and a second link to transmit unidirectional error-detection information. An encoder is to dynamically add first error-detection information to at least a portion of write data. A transmitter, coupled to the link interface, is to transmit the write data. A delay element is coupled to an output from the encoder. A receiver, coupled to the link interface, is to receive second error-detection information corresponding to at least the portion of the write data. Error-detection logic is coupled to an output from the delay element and an output from the receiver. The error-detection logic is to determine errors in at least the portion of the write data by comparing the first error-detection information and the second error-detection information, and, if an error is detected, is to assert an error condition.Type: GrantFiled: August 26, 2015Date of Patent: February 16, 2016Assignee: Rambus Inc.Inventors: Yuanlong Wang, Frederick A. Ware
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Patent number: 9262262Abstract: A controller includes a link interface that is to couple to a first link to communicate bidirectional data and a second link to transmit unidirectional error-detection information. An encoder is to dynamically add first error-detection information to at least a portion of write data. A transmitter, coupled to the link interface, is to transmit the write data. A delay element is coupled to an output from the encoder. A receiver, coupled to the link interface, is to receive second error-detection information corresponding to at least the portion of the write data. Error-detection logic is coupled to an output from the delay element and an output from the receiver. The error-detection logic is to determine errors in at least the portion of the write data by comparing the first error-detection information and the second error-detection information, and, if an error is detected, is to assert an error condition.Type: GrantFiled: September 14, 2015Date of Patent: February 16, 2016Assignee: Rambus Inc.Inventors: Yuanlong Wang, Frederick A. Ware
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Patent number: 9257163Abstract: A memory controller includes an interface to receive a data strobe signal and corresponding read data. The data strobe signal and the read data correspond to a read command issued by the memory controller, and the read data is received in accordance with the data strobe signal and an enable signal. A circuit in the memory controller is to dynamically adjust a timing offset between the enable signal and the data strobe signal, and control logic is to issue a supplemental read command in accordance with a determination that a time interval since a last read command issued by the memory controller exceeds a predetermined value.Type: GrantFiled: August 5, 2013Date of Patent: February 9, 2016Assignee: RAMBUS INC.Inventors: Bret Stott, Frederick A. Ware, Ian P. Shaeffer, Yuanlong Wang
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Publication number: 20160004594Abstract: A controller includes a link interface that is to couple to a first link to communicate bi-directional data and a second link to transmit unidirectional error-detection information. An encoder is to dynamically add first error-detection information to at least a portion of write data. A transmitter, coupled to the link interface, is to transmit the write data. A delay element is coupled to an output from the encoder. A receiver, coupled to the link interface, is to receive second error-detection information corresponding to at least the portion of the write data. Error-detection logic is coupled to an output from the delay element and an output from the receiver. The error-detection logic is to determine errors in at least the portion of the write data by comparing the first error-detection information and the second error-detection information, and, if an error is detected, is to assert an error condition.Type: ApplicationFiled: September 14, 2015Publication date: January 7, 2016Inventors: Yuanlong Wang, Frederick A. Ware
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Publication number: 20160004593Abstract: A controller includes a link interface that is to couple to a first link to communicate bidirectional data and a second link to transmit unidirectional error-detection information. An encoder is to dynamically add first error-detection information to at least a portion of write data. A transmitter, coupled to the link interface, is to transmit the write data. A delay element is coupled to an output from the encoder. A receiver, coupled to the link interface, is to receive second error-detection information corresponding to at least the portion of the write data. Error-detection logic is coupled to an output from the delay element and an output from the receiver. The error-detection logic is to determine errors in at least the portion of the write data by comparing the first error-detection information and the second error-detection information, and, if an error is detected, is to assert an error condition.Type: ApplicationFiled: September 14, 2015Publication date: January 7, 2016Inventors: Yuanlong Wang, Frederick A. Ware
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Publication number: 20150365108Abstract: A controller includes a link interface that is to couple to a first link to communicate bi-directional data and a second link to transmit unidirectional error-detection information. An encoder is to dynamically add first error-detection information to at least a portion of write data. A transmitter, coupled to the link interface, is to transmit the write data. A delay element is coupled to an output from the encoder. A receiver, coupled to the link interface, is to receive second error-detection information corresponding to at least the portion of the write data. Error-detection logic is coupled to an output from the delay element and an output from the receiver. The error-detection logic is to determine errors in at least the portion of the write data by comparing the first error-detection information and the second error-detection information, and, if an error is detected, is to assert an error condition.Type: ApplicationFiled: August 26, 2015Publication date: December 17, 2015Inventors: Yuanlong Wang, Frederick A. Ware
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Electrically erasable programmable memory device that generates a cyclic redundancy check (CRC) code
Patent number: 9213591Abstract: A controller includes a link interface that is to couple to a first link to communicate bi-directional data and a second link to transmit unidirectional error-detection information. An encoder is to dynamically add first error-detection information to at least a portion of write data. A transmitter, coupled to the link interface, is to transmit the write data. A delay element is coupled to an output from the encoder. A receiver, coupled to the link interface, is to receive second error-detection information corresponding to at least the portion of the write data. Error-detection logic is coupled to an output from the delay element and an output from the receiver. The error-detection logic is to determine errors in at least the portion of the write data by comparing the first error-detection information and the second error-detection information, and, if an error is detected, is to assert an error condition.Type: GrantFiled: August 11, 2015Date of Patent: December 15, 2015Assignee: Rambus Inc.Inventors: Yuanlong Wang, Frederick A. Ware -
ELECTRICALLY ERASABLE PROGRAMMABLE MEMORY DEVICE THAT GENERATES A CYCLIC REDUNDANCY CHECK (CRC) CODE
Publication number: 20150347223Abstract: A controller includes a link interface that is to couple to a first link to communicate bi-directional data and a second link to transmit unidirectional error-detection information. An encoder is to dynamically add first error-detection information to at least a portion of write data. A transmitter, coupled to the link interface, is to transmit the write data. A delay element is coupled to an output from the encoder. A receiver, coupled to the link interface, is to receive second error-detection information corresponding to at least the portion of the write data. Error-detection logic is coupled to an output from the delay element and an output from the receiver. The error-detection logic is to determine errors in at least the portion of the write data by comparing the first error-detection information and the second error-detection information, and, if an error is detected, is to assert an error condition.Type: ApplicationFiled: August 11, 2015Publication date: December 3, 2015Inventors: Yuanlong Wang, Frederick A. Ware -
Publication number: 20150349798Abstract: A controller includes a link interface that is to couple to a first link to communicate bi-directional data and a second link to transmit unidirectional error-detection information. An encoder is to dynamically add first error-detection information to at least a portion of write data. A transmitter, coupled to the link interface, is to transmit the write data. A delay element is coupled to an output from the encoder. A receiver, coupled to the link interface, is to receive second error-detection information corresponding to at least the portion of the write data. Error-detection logic is coupled to an output from the delay element and an output from the receiver. The error-detection logic is to determine errors in at least the portion of the write data by comparing the first error-detection information and the second error-detection information, and, if an error is detected, is to assert an error condition.Type: ApplicationFiled: August 11, 2015Publication date: December 3, 2015Inventors: Yuanlong Wang, Frederick A. Ware
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Publication number: 20150324250Abstract: A controller includes a link interface that is to couple to a first link to communicate bi-directional data and a second link to transmit unidirectional error-detection information. An encoder is to dynamically add first error-detection information to at least a portion of write data. A transmitter, coupled to the link interface, is to transmit the write data. A delay element is coupled to an output from the encoder. A receiver, coupled to the link interface, is to receive second error-detection information corresponding to at least the portion of the write data. Error-detection logic is coupled to an output from the delay element and an output from the receiver. The error-detection logic is to determine errors in at least the portion of the write data by comparing the first error-detection information and the second error-detection information, and, if an error is detected, is to assert an error condition.Type: ApplicationFiled: July 22, 2015Publication date: November 12, 2015Inventors: Yuanlong Wang, Frederick A. Ware
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Publication number: 20150309924Abstract: A control apparatus with multiple flash memory card channels includes a host side port unit, an instruction data processing unit, and flash memory card port units. The host side port unit exchanges a host side instruction and host side read/write data with a high-speed serial communication protocol host side. The flash memory card port units respectively exchange flash memory card instructions and flash memory card read/write data with a plurality of flash memory cards. An instruction from the high-speed serial communication protocol host side is divided into multiple sub-instructions to be respectively transmitted to the flash memory card port units and exchange of instruction and data with a plurality of flash memory cards is carried out in a coincident period of time so as to achieve the purposes of expanding access capacity and increasing access speed, reducing the operation cost of products, and enhancing flexibility of use of flash memory cards.Type: ApplicationFiled: July 26, 2013Publication date: October 29, 2015Inventors: Miao Chen, Yuanlong Wang
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Patent number: 9092352Abstract: A controller includes a link interface that is to couple to a first link to communicate bi-directional data and a second link to transmit unidirectional error-detection information. An encoder is to dynamically add first error-detection information to at least a portion of write data. A transmitter, coupled to the link interface, is to transmit the write data. A delay element is coupled to an output from the encoder. A receiver, coupled to the link interface, is to receive second error-detection information corresponding to at least the portion of the write data. Error-detection logic is coupled to an output from the delay element and an output from the receiver. The error-detection logic is to determine errors in at least the portion of the write data by comparing the first error-detection information and the second error-detection information, and, if an error is detected, is to assert an error condition.Type: GrantFiled: February 7, 2014Date of Patent: July 28, 2015Assignee: RAMBUS INC.Inventors: Yuanlong Wang, Frederick A. Ware
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Publication number: 20140223269Abstract: A controller includes a link interface that is to couple to a first link to communicate bi-directional data and a second link to transmit unidirectional error-detection information. An encoder is to dynamically add first error-detection information to at least a portion of write data. A transmitter, coupled to the link interface, is to transmit the write data. A delay element is coupled to an output from the encoder. A receiver, coupled to the link interface, is to receive second error-detection information corresponding to at least the portion of the write data. Error-detection logic is coupled to an output from the delay element and an output from the receiver. The error-detection logic is to determine errors in at least the portion of the write data by comparing the first error-detection information and the second error-detection information, and, if an error is detected, is to assert an error condition.Type: ApplicationFiled: February 7, 2014Publication date: August 7, 2014Applicant: Rambus Inc.Inventors: Yuanlong Wang, Frederick A. Ware