Abstract: A driver circuit of a display apparatus is provided with a nor circuit in each output line of a timing pulse. To the nor circuit, inputted are a timing pulse to be supplied to the output line and a pre-charge pulse for pre-charging a data signal line SL to which a write signal is being inputted based on the timing pulse. With this structure, it is possible to realize a driver circuit storing a pre-charge circuit of a display apparatus, which can surely prevent a collision between a pre-charge potential and a potential of a video signal in a signal supply line when pre-charging the signal supply line from a pre-charge power supply of a small driving performance, while maintaining the number of stages in the shift register to be the required minimum number.

Abstract: In one embodiment of the present invention, a unit circuit of a shift register includes a bootstrap circuit configured with a transistor T1, a transistor T2 and a capacitor, a transistor T3, a transistor T4, and a reset signal generation circuit. By use of two-phase clock signals whose high level periods do not overlap with each other, the reset signal generation circuit generates a reset signal which is at a high level in a normal state and changes to a low level when an input signal turns into the high level. During a period that the reset signal is at the high level, transistors perform discharge of a node and pull-down of an output signal. Thus, it is possible to obtain a shift register which performs discharge of a node and pull-down of an output signal and achieves a small area and low power consumption without using an output signal from a subsequent circuit.

Abstract: In one embodiment of the present invention, a unit circuit of a shift register includes a bootstrap circuit configured with a transistor T1, a transistor T2 and a capacitor, a transistor T3, a transistor T4, and a reset signal generation circuit. By use of two-phase clock signals and whose high level periods do not overlap with each other, the reset signal generation circuit generates a reset signal which is at a high level in a normal state and changes to a low level when an input signal turns into the high level. During a period that the reset signal is at the high level, transistors T3 and T4 perform discharge of a node and pull-down of an output signal. Thus, it is possible to obtain a power-saving shift register that fixes an output signal at a low level in a normal state without allowing a through current to flow therein.

Abstract: In each horizontal period, by switching ON switches respectively provided for three data signal lines for R, G and B in a group at the same time only in a predetermined period, the data signal lines in the group are preliminary charged to a predetermined potential at the same time before a data signal supply period. In a subsequent data signal supply period, respective switches of data signal lines for R, G and B are switched ON sequentially, to sequentially supply respective data for R, G and B to pixels on a scanning signal line as selected are supplied via data signal lines. As a result, in a display device driven by time-division based on a group of sequentially provided data signal lines, it is possible to suppress up-throw potential fluctuations when display.

Abstract: A shift register includes control circuits CNi (i=1 through n) corresponding to respective blocks, and a level shifter LSi+1 of the next stage is controlled by one of the outputs of the shift register and one of the outputs of flip-flops Fi. With this, a level shifter of the present stage operates only for a period minimum for outputting the shift output from the present block, so that the power consumption is reduced, Furthermore, it is possible to cause the outputs SL1 through SLn not to overlap each other.

Abstract: In one embodiment of the present invention, a source driver includes a shift register including latch stages each including a level shifter that level-shifts clock signals so that the signals are fed into a set-reset flip-flop as inverted set input signals. Outputs from the set-reset flip-flop are delayed by a hazard preventing circuit and then fed into a level shifter in the next latch stage as enable signals. A delay trimming circuit causes a NAND circuit to perform a NAND operation with respect to outputs obtained by a delay of the outputs by a delay circuit and outputs from the level shifter in the next latch stage, so that a sampling pulse is derived. This allows for provision of a pulse output circuit capable of further trimming delay in output pulses and of securing a sufficient interval between the output pulses.

Abstract: While an output signal of a flip-flop is inactive in a shift register, NAND circuits of clock pulse extracting sections prevent the performing of conduction switching operation in accordance with periodic level change of clock signals between a logical derivation path for High output and a logical derivation path for Low output, by input of the output signal.

Abstract: A liquid crystal display apparatus (1) wherein the shift registers of a source driver (4) are configured by use of asynchronous RS flip-flops in which an active input to a set input terminal has a higher priority than an active input to a reset terminal. In a second mode of operation, first and second clock signals and a start pulse are fixed at high levels, thereby performing discharges from all the pixels (PIX) of a liquid crystal panel (2).

Abstract: The subject invention provides a drive circuit for a display apparatus, comprising: a shift register; and a pulse generation circuit for generating a drive pulse signal using an output pulse signal generated in the shift register, wherein: the pulse generation circuit forms a pulse-starting edge and a pulse-termination edge of the drive pulse signal using a rise or a fall of pulse resulting from activation of the output pulse signal. On this account, pulse generation can be performed with high accuracy in a pulse generation circuit used for a drive circuit for a display apparatus or the like.

Abstract: In one embodiment of the present invention, the present shift register is a shift register provided in a display device by which a partial-screen display is available. The shift register includes a shift stopping circuit that is provided in an in-between stage, and stops operation of the shift register between a first stage and a last stage of the shift register in partial-screen display. The shift register also includes a circuit that is provided in a stage other than the in-between stage in such a manner that the circuit does not perform signal processing but serves as a signal path. The circuit is same as the shift stopping circuit in configuration. The foregoing allows improvement in display quality of the display device employing the present shift register.

Abstract: In one embodiment of the present invention, on each source bus line, an electric charge escaping transistor is provided having the same polarity as a pixel transistor and having a gate to which a turn-off voltage signal of the pixel transistor is supplied. When an active matrix liquid crystal display device is powered off, the turn-off voltage signal is made to reach the GND level before a turn-on voltage signal of the pixel transistor reaches the GND level, so that the pixel transistor and the electric charge escaping transistor are made half-open. This lets electric charges accumulated in the pixel escape to a common electrode TCOM.

Abstract: In a shift register of the present invention, each of flip-flops has a phase difference detection section and a waveform timing forming section as a malfunction prevention circuit. The phase difference detection section detects an overlapping waveform caused by a phase difference between clock signals SCK and SCKB, and generates an output signal A (A1, A2, . . . ) from which the overlapping portions are removed. The waveform timing forming section outputs an output signal X (X1, X2, . . . ) obtained by extracting a period when the output signal A (A1, A2, . . . ) generated in a corresponding phase difference detection section is High, when an output signal Q (Q1, Q2, . . . ) from a corresponding flip-flop is High. The output signal X (X1, X2, . . . ) sets a flip-flop in a following stage.

Abstract: A driving circuit of a display device is disclosed in accordance with an embodiment of the present invention creates a non-display area on a display section of the display device so that a partial-screen display becomes available. The driving circuit includes a shift register and a signal processing circuit that processes a signal tapped off from the shift register. In partial-screen display, the signal processing circuit interrupts a signal tapped off from a predetermined stage of the shift register. This makes it possible to realize a driving circuit of a display device by which a high-quality display is possible with a small circuit area.

Abstract: A latch section includes a latch circuit. The latch circuit includes inverters and latches an input signal from a gating section. Between one of the inverters of the latch circuit and the output terminal OUT is disposed an analog switch whose ON/OFF characteristics are switched according to High/Low of a reset signal. Between the output terminal and an input for receiving a low potential as a power supply of a flip-flop is disposed a switching element whose ON/OFF characteristics are switched according to High/Low of the reset signal.

Abstract: In an embodiment, a sampling signal to each data signal line is generated by using an output signal outputted from each flip-flop, and a precharge signal by which the data signal line to which the sampling signal is to be outputted is precharged is generated by using an output signal outputted from an output terminal of the flip-flop. Further, by providing a NOR circuit, an active period of the precharge signal and an active period of the sampling signal are prevented from overlapping each other. With this, in an embodiment of a display device driving circuit, including a precharge circuit, which causes a precharge power supply to precharge signal supply lines, the number of shift registers and the size of a circuit can be reduced.

Abstract: A driving device of a display device includes: a data signal line driving circuit, provided with a shift register having a level shifter for boosting a source clock signal so as to apply the source clock signal to a flip-flop, which causes a sampling circuit to directly sample a multi-gradation data signal based on each output from the shift register so as to output the multi-gradation data signal to each of a plurality of data signal lines; a control circuit for switching a full-screen display mode in which a whole of the display screen performs display and a partial-screen display mode in which only a part of the display screen performs time-sharing display; a data generating section for generating a constant voltage data writing signal made of a constant voltage; and a control circuit for outputting a selection signal for causing a nondisplay portion to directly sample the constant voltage data writing signal from the constant voltage data writing signal generation means so as to output the constant voltag

Abstract: The subject invention discloses a scanning direction control circuit, which includes a bidirectional shift register in which shifting direction is switched in accordance with a switching signal L/R, which is step-upped by a level shifter when having lower amplitude than the driving voltage. The scanning direction control circuit includes a latch circuit between the level shifter and the bidirectional shift register, and a control circuit causes the latch circuit to carry out latching operation after shifting operation of flip-flops constituting the bidirectional shift register is completed in response to output signals of the flip-flops. The control circuit brings the level shifter into active state in a period before, at and after the latching timing, and brings the level shifter into inactive state in the remaining period. With this arrangement, the switching signal L/R can be supplied at a predetermined timing regardless of external input timing thereof, with low power consumption.

Abstract: A level shift circuit includes first and second level shifters which respectively output first and second output signals that are produced by level shifting two kinds of input clock signals whose high level periods do not overlap. The level shift circuit also includes control transistors and control lines which, together, prevent a feedthrough current from flowing into the second level shifter when the first output signal is high level, and prevent a feedthrough current from flowing into the first level shifter when the second output signal is high level, so as to suspend the level shift operation of the first and second level shifters. With the level shift circuit, power consumption during a specific time period in a non-active period of the clock signal can be eliminated, where the specific time period of one clock signal is the active period of the other clock signal.

Abstract: A level shift circuit includes first and second level shifters which respectively output first and second output signals that are produced by level shifting two kinds of input clock signals whose high level periods do not overlap. The level shift circuit also includes control transistors and control lines which, together, prevent a feedthrough current from flowing into the second level shifter when the first output signal is high level, and prevent a feedthrough current from flowing into the first level shifter when the second output signal is high level, so as to suspend the level shift operation of the first and second level shifters. With the level shift circuit, power consumption during a specific time period in a non-active period of the clock signal can be eliminated, where the specific time period of one clock signal is the active period of the other clock signal.

Abstract: A driving device of a display device includes: a data signal line driving circuit, provided with a shift register having a level shifter for boosting a source clock signal so as to apply the source clock signal to a flip-flop, which causes a sampling circuit to directly sample a multi-gradation data signal based on each output from the shift register so as to output the multi-gradation data signal to each of a plurality of data signal lines; a control circuit for switching a full-screen display mode in which a whole of the display screen performs display and a partial-screen display mode in which only a part of the display screen performs time-sharing display; a data generating section for generating a constant voltage data writing signal made of a constant voltage; and a control circuit for outputting a selection signal for causing a nondisplay portion to directly sample the constant voltage data writing signal from the constant voltage data writing signal generation means so as to output the constant voltag