Abstract: In one embodiment of the present invention, a unit circuit of a shift register includes a bootstrap circuit configured with a transistor T1, a transistor T2 and a capacitor, a transistor T3, a transistor T4, and a reset signal generation circuit. By use of two-phase clock signals and whose high level periods do not overlap with each other, the reset signal generation circuit generates a reset signal which is at a high level in a normal state and changes to a low level when an input signal turns into the high level. During a period that the reset signal is at the high level, transistors T3 and T4 perform discharge of a node and pull-down of an output signal. Thus, it is possible to obtain a power-saving shift register that fixes an output signal at a low level in a normal state without allowing a through current to flow therein.

Abstract: A signal processing circuit of the present invention includes: a first input terminal; a second input terminal; a third input terminal; a first node; a second node; an output terminal; a resistor; a first signal generating section which (i) is connected to the first node, a third input terminal, and the output terminal and (ii) includes a bootstrap capacitor; and a second signal generating section which is connected to the second node, a first power supply, and the output terminal. The first node becomes active in a case where the first input terminal becomes active. The second node becomes active in a case where the second input terminal becomes active. The output terminal is connected to the first power supply via the resistor. With the configuration, it is possible to have an improvement in operational stability of the signal processing circuit.

Abstract: A signal processing circuit of the present invention includes: first and second input terminals; an output terminal; a bootstrap capacitor; a first output section connected to the second input terminal and the output terminal; a second output section connected to the first input terminal, a first power source, and the output terminal; and an electric charge control section for controlling the electric charge of the bootstrap capacitor, the electric charge control section being connected to the first input terminal, the electric charge control section and the first output section being connected to each other via a relay section for either electrically connecting the electric charge control section and the first output section to each other or electrically blocking the electric charge control section and the first output section from each other, the electric charge control section including a resistor connected to a second power source.

Abstract: A flip-flop of the present invention includes: an input terminal; an output terminal; a first control signal terminal and a second control signal terminal; a first output section including a bootstrap capacitor, the first output section being connected to the first control signal terminal and the output terminal; a second output section connected to a first output section source and the output terminal; a first input section connected to the input terminal, the first input section charging the bootstrap capacitor; a discharge section discharging the bootstrap capacitor; a second input section connected to the input terminal, the second input section being also connected to the second output section; a reset section controlling the discharge section and the second output section, the reset section being connected to the second control signal terminal; a first initialization section controlling the first output section; a second initialization section controlling the first input section; and a third initializat

Abstract: A semiconductor device (10) provided with at least a plurality of transistors and bootstrap capacitors (Ca1 and Cb1), the semiconductor device (10) includes: a semiconductor layer (22) made of the same material as a channel layer of each of the transistors; a capacitor electrode (24) formed in an upper layer of the semiconductor layer (22); and a clock signal line (17) formed in an upper layer of the capacitor electrode (24), the capacitor electrode (24) being connected to a gate electrode of each of the transistors, the clock signal line (17) being supplied with a clock signal (CK) from outside the semiconductor device (10), the capacitors (Ca1 and Cb1) each being formed in an overlap section where the semiconductor layer (22), the gate insulating film (23) and the capacitor electrode (24) overlap one another, the overlap section and the clock signal line (17) overlapping each other when viewed from above.

Abstract: A unit circuit (11) includes: a transistor (T2) having its drain terminal to be supplied with a clock signal (CK) and its source terminal connected to an output terminal (OUT); a transistor (T9) which, when supplied with an active all-on control signal (AON), outputs an ON voltage to the output terminal (OUT), and which, when supplied with a nonactive all-on control signal (AONB), stops outputting the ON voltage; a transistor (T1) which supplies the ON voltage to a control terminal of the transistor (T2) in accordance with an input signal (IN); a transistor (T4) which, when supplied with the active all-on control signal (AON), supplies an OFF voltage to a control terminal of the transistor (T2). This makes it possible to provide a shift register of a simple structure that can prevent a malfunction from occurring after all-on operation, and to provide a display device.

Abstract: A transistor circuit includes at least one transistor, wherein at least part of a connecting portion that connects the transistor (Tr1) and a power supply line (33) is formed from a material of which a channel of the transistor (Tr1) is made. This configuration reduces a circuit area of the transistor circuit.

Abstract: At least one embodiment the present invention a plurality of unit circuits connected in multiple stages, to normal operation when the unit circuits are simultaneously turned on to output high-level output signals. When a shift register malfunctions, so that output signals provided by previous- and subsequent-stage unit circuits are simultaneously set to high level, malfunction restoration circuits and included in a unit circuit detect the malfunction in at least one embodiment. The malfunction restoration circuit provides a high voltage to a node, thereby forcibly pulling down an output signal. Also, the malfunction restoration circuit forcibly discharges another node, so that a charge accumulated in a capacitance is released. As a result, the shift register in malfunction can be instantaneously restored to normal operation. At least one embodiment of the present invention is suitable for driver circuits or suchlike of display devices and imaging devices.

Abstract: A signal generator circuit of the present invention is a signal generator circuit for use in a display device, the display device including (a) a pixel having a pixel electrode, (b) an electric conductor with which the pixel electrode forms a capacitor, (c) a data signal line driving circuit which outputs a data signal whose polarity is reversed for each n horizontal scanning period(s), where n is a natural number, and (d) a scanning signal line driving circuit which outputs scanning signals corresponding to respective stages, said signal generator circuit generating a drive signal supplied to the electric conductor, wherein: said signal generator circuit comprises flip flops corresponding to the respective stages, each flip flop including a gate circuit and a latch circuit; and in regard to one flip flop corresponding to one of the stages, (i) the gate circuit is supplied with a signal synchronized with a scanning signal corresponding to a preceding stage of the one of the stages, and a signal synchronized w

Abstract: A single-phase input including transistors all of which have only a single type of channel polarity, which buffer includes: a buffer section 32, including a first series circuit formed by two n-channel transistors connected to each other in series, a second series circuit formed by two n-channel transistors connected to each other in series at a connection point OUT, and a capacitor; and an inverted-signal generating section for generating an inverted-signal from an input signal, the inverted-signal generating section including n-channel transistors but no p-channel transistor, the input signal being inputted to respective gates of the transistors, the inverted-signal being inputted to a gate of the transistor 4, and an output signal being outputted via the connection point OUT. With the buffer, it is possible that a consumption current be reduced and a current drive for a load is enhanced.

Abstract: A signal output circuit of the present invention is provided in a unit stage of a shift register. The signal output circuit includes a set-reset flip-flop, and a signal generation circuit for generating an output signal by loading or blocking a clock signal in accordance with a signal inputted thereto. The signal output circuit is arranged such that: the signal generation circuit receives a signal outputted from the flip-flop and the output signal fed back to the signal generating circuit; and the output signal is fed back to a reset input of the flip-flop. This makes it possible to achieve a reduction in the area of the circuit and a simplification of the circuit.

Abstract: A circuit is constituted by a plurality of n-channel-type transistors, the circuit including: among the plurality of transistors, a transistor including a drain terminal for receiving a voltage of VDD, a source terminal, and a gate terminal for receiving an input signal; among the plurality of transistors, a transistor including a drain terminal for receiving the voltage of VDD, a source terminal connected to an output terminal, and a gate terminal connected to the source terminal of the transistor; and a capacitor provided between a node and a clock terminal for receiving a clock signal. In at least one embodiment, the clock signal inputted into the clock terminal has a frequency higher than that of an output signal outputted from the output terminal.

Abstract: While an output signal of a flip-flop is inactive in a shift register, NAND circuits of clock pulse extracting sections prevent the performing of conduction switching operation in accordance with periodic level change of clock signals between a logical derivation path for High output and a logical derivation path for Low output, by input of the output signal.

Abstract: A signal output circuit of one embodiment of the present invention is provided in a unit stage of a shift register. The signal output circuit includes a set-reset flip-flop, and a signal generation circuit for generating an output signal by loading or blocking a clock signal in accordance with a signal inputted thereto. The signal output circuit is arranged such that: the signal generation circuit receives a signal outputted from the flip-flop and the output signal fed back to the signal generating circuit; and the output signal is fed back to a reset input of the flip-flop. This makes it possible to achieve a reduction in the area of the circuit and a simplification of the circuit.

Abstract: In one embodiment of the present invention, a source driver includes a shift register including latch stages each including a level shifter that level-shifts clock signals so that the signals are fed into a set-reset flip-flop as inverted set input signals. Outputs from the set-reset flip-flop are delayed by a hazard preventing circuit and then fed into a level shifter in the next latch stage as enable signals. A delay trimming circuit causes a NAND circuit to perform a NAND operation with respect to outputs obtained by a delay of the outputs by a delay circuit and outputs from the level shifter in the next latch stage, so that a sampling pulse is derived. This allows for provision of a pulse output circuit capable of further trimming delay in output pulses and of securing a sufficient interval between the output pulses.

Abstract: A shift register includes a plurality of stages of unit circuits each including a flip-flop. Each of the unit circuits generates, by obtaining a sync signal in accordance with an output from the flip-flop, an output signal. The flip-flop includes a first switch and a second switch and a latch circuit for latching a signal supplied thereto and outputting the signal as the output from the flip-flop. A first shift direction signal is supplied to the latch circuit via the first switch, and the second shift direction signal is supplied to the latch circuit via the second switch. In each unit circuit other than those of the first and last stages, an output signal from a previous stage is supplied to a control terminal of the first switch, and an output signal from a subsequent stage is supplied to a control terminal of the second switch.

Abstract: In one embodiment of the present invention, a unit circuit of a shift register includes a bootstrap circuit configured with a transistor T1, a transistor T2 and a capacitor, a transistor T3, a transistor T4, and a reset signal generation circuit. By use of two-phase clock signals and whose high level periods do not overlap with each other, the reset signal generation circuit generates a reset signal which is at a high level in a normal state and changes to a low level when an input signal turns into the high level. During a period that the reset signal is at the high level, transistors T3 and T4 perform discharge of a node and pull-down of an output signal. Thus, it is possible to obtain a power-saving shift register that fixes an output signal at a low level in a normal state without allowing a through current to flow therein.

Abstract: An embodiment of the present invention provides a power supply circuit including a charge-pumping booster section which uses switching elements provided only by N-channel transistors yet does not have a problem of voltage drop by threshold value. When a boosted voltage is obtained at a first terminal of a first capacitor in a booster section, a booster control section supplies this boosted voltage to a third capacitor, to boost the voltage further thereby turning ON a first transistor. When a boosted voltage is obtained at a first terminal of a second capacitor in the booster section, the booster control section supplies this boosted voltage to a fourth capacitor, to boost the voltage further thereby turning ON a second transistor. This arrangement eliminates a problem of voltage drop by threshold value in the first and the second transistors which serve as output-side switching elements.

Abstract: A one-input and three-output demultiplexer that includes sampling switches for sampling a video signal is provided at one end side of source bus lines, and a one-input and three-output demultiplexer that includes test switches provided corresponding to sampling switches and that uses a test video signal as an input signal is provided at the other end side of the source bus lines. When an any control signal out of three control signals for controlling states of a sampling switch and a test switch is defined as a target control signal, a source bus line connected to the sampling switch which is set to an on state by the target control signal and a source bus line connected to the test switch which is set to an on state by the target control signal are different.

Abstract: In one embodiment of the present invention, a unit circuit of a shift register includes a bootstrap circuit configured with a transistor T1, a transistor T2 and a capacitor, a transistor T3, a transistor T4, and a reset signal generation circuit. By use of two-phase clock signals whose high level periods do not overlap with each other, the reset signal generation circuit generates a reset signal which is at a high level in a normal state and changes to a low level when an input signal turns into the high level. During a period that the reset signal is at the high level, transistors perform discharge of a node and pull-down of an output signal. Thus, it is possible to obtain a shift register which performs discharge of a node and pull-down of an output signal and achieves a small area and low power consumption without using an output signal from a subsequent circuit.