Abstract: A method for processing a semiconductor wafer comprises: preparing a semiconductor wafer including a main body and a rim, the rim having a greater thickness than the main body and including a projection projecting; supporting the semiconductor wafer with a holding tape; preparing a base including a stage and an outer portion; setting the semiconductor wafer on the base so that the main body is supported by a support surface of the stage; and separating the main body and the rim by cutting an edge portion of the main body in a state in which the main body is supported by the stage. The setting the semiconductor wafer on the base includes setting the semiconductor wafer on the base so that the main body is supported by the stage in a state in which the projection is separated from a head surface of the outer portion of the base.

Abstract: A polyester elastomer resin composition for resin belt materials contains 80-92.99% by weight of a thermoplastic polyester elastomer (A), 7-19.99% by weight of glass fibers (B) and 0.01-5.0% by weight of a crystal nucleator (C), and which is also characterized in that: the thermoplastic polyester elastomer (A) is a polyester block copolymer which contains 40-70% by weight of a high melting point crystalline polymer segment (a1) that is composed of a crystalline aromatic polyester unit and 30-60% by weight of a low melting point polymer segment (a2) that is composed of an aliphatic polyether unit; and the melt flow rate as determined in accordance with ASTM D1238 at 230° C. under a load of 2,160 g is 1.0 g/10 min or more but less than 10.0 g/10 min.

Abstract: The semiconductor device according to the present invention includes a ferroelectric film and an electrode stacked on the ferroelectric film. The electrode has a multilayer structure of an electrode lower layer in contact with the ferroelectric film and an electrode upper layer stacked on the electrode lower layer. The electrode upper layer is made of a conductive material having an etching selection ratio with respect to the materials for the ferroelectric film and the electrode lower layer. The upper surface of the electrode upper layer is planarized.

Abstract: A polyester elastomer resin composition for resin belt materials contains 80-92.99% by weight of a thermoplastic polyester elastomer (A), 7-19.99% by weight of glass fibers (B) and 0.01-5.0% by weight of a crystal nucleator (C), and which is also characterized in that: the thermoplastic polyester elastomer (A) is a polyester block copolymer which contains 40-70% by weight of a high melting point crystalline polymer segment (a1) that is composed of a crystalline aromatic polyester unit and 30-60% by weight of a low melting point polymer segment (a2) that is composed of an aliphatic polyether unit; and the melt flow rate as determined in accordance with ASTM D1238 at 230° C. under a load of 2,160 g is 1.0 g/10 min or more but less than 10.0 g/10 min.

Abstract: The semiconductor device according to the present invention includes a ferroelectric film and an electrode stacked on the ferroelectric film. The electrode has a multilayer structure of an electrode lower layer in contact with the ferroelectric film and an electrode upper layer stacked on the electrode lower layer. The electrode upper layer is made of a conductive material having an etching selection ratio with respect to the materials for the ferroelectric film and the electrode lower layer. The upper surface of the electrode upper layer is planarized.

Abstract: The semiconductor device according to the present invention includes a ferroelectric film and an electrode stacked on the ferroelectric film. The electrode has a multilayer structure of an electrode lower layer in contact with the ferroelectric film and an electrode upper layer stacked on the electrode lower layer. The electrode upper layer is made of a conductive material having an etching selection ratio with respect to the materials for the ferroelectric film and the electrode lower layer. The upper surface of the electrode upper layer is planarized.

Abstract: A semiconductor device is provided with a substrate made of a semiconductor material, an interconnect layer, at least one electronic element, and a sealing resin. The substrate has a main surface and a pair of lateral surfaces that are orthogonal to the main surface and face in opposite directions to each other. A recessed portion that is recessed from the main surface and has an opening portion that opens on at least one of the pair of lateral surfaces is formed in the substrate. The interconnect layer is formed on the substrate. The electronic element is an orientation sensor, for example, and is accommodated in the recessed portion of the substrate. The sealing resin covers the electronic element.

Abstract: A semiconductor device includes a substrate that is made of a semiconductor material and has a main surface formed with a recess. The semiconductor device also includes a wiring layer formed on the substrate, an electronic element housed in the recess, and a sealing resin covering at least a part of the electronic element.

Abstract: A semiconductor device is provided with a substrate made of a semiconductor material, an interconnect layer, at least one electronic element, and a sealing resin. The substrate has a main surface and a pair of lateral surfaces that are orthogonal to the main surface and face in opposite directions to each other. A recessed portion that is recessed from the main surface and has an opening portion that opens on at least one of the pair of lateral surfaces is formed in the substrate. The interconnect layer is formed on the substrate. The electronic element is an orientation sensor, for example, and is accommodated in the recessed portion of the substrate. The sealing resin covers the electronic element.

Abstract: A semiconductor device is provided with a substrate made of a semiconductor material, an interconnect layer, at least one electronic element, and a sealing resin. The substrate has a main surface and a pair of lateral surfaces that are orthogonal to the main surface and face in opposite directions to each other. A recessed portion that is recessed from the main surface and has an opening portion that opens on at least one of the pair of lateral surfaces is formed in the substrate. The interconnect layer is formed on the substrate. The electronic element is an orientation sensor, for example, and is accommodated in the recessed portion of the substrate. The sealing resin covers the electronic element.

Abstract: A semiconductor storage device includes an insulating layer. A ferroelectric capacitor is on the insulating layer and includes a lower electrode, a ferroelectric film, and an upper electrode. An interlayer insulating film is formed on the insulating layer, and has an opening where the ferroelectric capacitor is disposed. A first metal plug is formed in the insulating layer and connected to the lower electrode via the opening. A second metal plug is embedded in the insulating layer outside the ferroelectric capacitor. A hydrogen barrier film covers the ferroelectric capacitor and the interlayer insulating film. An upper surface of the interlayer insulating film is higher than an upper surface of the first metal plug so that a step is therebetween. The lower electrode is formed on the upper surface of the interlayer insulating film, the upper surface of the first metal plug and the step.

Abstract: A semiconductor device includes a lower electrode, a ferroelectric film on the lower electrode, an upper electrode on the ferroelectric film, and a first insulating film covering a surface and a side of the upper electrode, a side of the ferroelectric film, and a side of the lower electrode. The first insulating film includes a first opening that exposes a portion of the surface of the upper electrode. A second insulating film covers the first insulating film and includes a second opening that exposes the portion of the surface of the upper electrode through a second opening. A barrier metal is formed in the first opening and the second opening, and is connected to the upper electrode. A connection region in which a material of the barrier metal interacts with a material of the upper electrode extends below an upper-most surface of the upper electrode.

Abstract: A semiconductor device includes a semiconductor substrate, a first insulating layer laminated on the semiconductor substrate, a first metal wiring pattern embedded in a wire-forming region of the first insulating layer, a second insulating layer laminated on the first insulating layer, a second metal wiring pattern embedded in a wire-forming region of the second insulating layer and first dummy metal patterns embedded each in a wire-opposed region opposing to the wire-forming region of the second insulating layer and in a non-wire-opposed region opposing to a non-wire-forming region other than the wire-forming region of the second insulating layer, the wire-opposed region and the non-wire-opposed region each in a non-wire-forming region other than the wire-forming region of the first insulating layer.

Abstract: A semiconductor device according to the present invention includes a semiconductor substrate, and an interlayer dielectric film, formed on the semiconductor substrate, having a multilayer structure of a compressive stress film and a tensile stress film.

Abstract: A semiconductor storage device includes an insulating layer. A ferroelectric capacitor is on the insulating layer and includes a lower electrode, a ferroelectric film, and an upper electrode. An interlayer insulating film is formed on the insulating layer, and has an opening where the ferroelectric capacitor is disposed. A first metal plug is formed in the insulating layer and connected to the lower electrode via the opening. A second metal plug is embedded in the insulating layer outside the ferroelectric capacitor. A hydrogen barrier film covers the ferroelectric capacitor and the interlayer insulating film. An upper surface of the interlayer insulating film is higher than an upper surface of the first metal plug so that a step is therebetween. The lower electrode is formed on the upper surface of the interlayer insulating film, the upper surface of the first metal plug and the step.

Abstract: A semiconductor device includes a lower wiring layer made of a conductive material; an upper wiring layer formed in an upper layer than the lower wiring layer; and a fuse film, at least a portion of the fuse film being formed in a plug formation layer in which a plug for connecting the lower wiring layer and the upper wiring layer is formed, and made of a conductive material including a metallic material other than copper.

Abstract: A semiconductor storage device includes an insulating layer. A ferroelectric capacitor is on the insulating layer and includes a lower electrode, a ferroelectric film, and an upper electrode. An interlayer insulating film is formed on the insulating layer, and has an opening where the ferroelectric capacitor is disposed. A first metal plug is formed in the insulating layer and connected to the lower electrode via the opening. A second metal plug is embedded in the insulating layer outside the ferroelectric capacitor. A hydrogen barrier film covers the ferroelectric capacitor and the interlayer insulating film. An upper surface of the interlayer insulating film is higher than an upper surface of the first metal plug so that a step is therebetween. The lower electrode is formed on the upper surface of the interlayer insulating film, the upper surface of the first metal plug and the step.

Abstract: A method for manufacturing a semiconductor storage device includes forming a first insulating film on a semiconductor substrate; forming a first conductive layer; forming a trench in the semiconductor substrate and the first conductive layer by etching; forming a deposition layer by depositing an insulating material in the trench; removing by etching a side portion of the deposition layer to form a side surface that has a flat surface and a curved surface with a lower edge that is in contact with a side surface of the first conductive layer and to form a gap between the curved and the side surfaces; forming a second conductive layer; removing the deposition layer until at least the curved surface of the side surface is exposed to form an embedded insulator in the trench; forming a second insulating film; and forming a control gate on the embedded insulator and the second insulating film.

Abstract: A semiconductor device includes a lower electrode, a ferroelectric film on the lower electrode, an upper electrode on the ferroelectric film, and a first insulating film covering a surface and a side of the upper electrode, a side of the ferroelectric film, and a side of the lower electrode. The first insulating film includes a first opening that exposes a portion of the surface of the upper electrode. A second insulating film covers the first insulating film and includes a second opening that exposes the portion of the surface of the upper electrode through a second opening. A barrier metal is formed in the first opening and the second opening, and is connected to the upper electrode. A connection region in which a material of the barrier metal interacts with a material of the upper electrode extends below an upper-most surface of the upper electrode.

Abstract: The semiconductor device according to the present invention includes a semiconductor layer, an interlayer dielectric film formed on the semiconductor layer, a wire formed on the interlayer dielectric film with a metallic material to have a width of not more than 0.4 ?m, and a broad portion integrally formed on the wire to extend from the wire in the width direction thereof.