Patents by Inventor Yuichi Nakao

Yuichi Nakao has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 8912657
    Abstract: The semiconductor device according to the present invention includes a semiconductor substrate, a first insulating layer laminated on the semiconductor substrate, a first metal wiring pattern embedded in a wire-forming region of the first insulating layer, a second insulating layer laminated on the first insulating layer, a second metal wiring pattern embedded in a wire-forming region of the second insulating layer and first dummy metal patterns embedded each in a wire-opposed region opposing to the wire-forming region of the second insulating layer and in a non-wire-opposed region opposing to a non-wire-forming region other than the wire-forming region of the second insulating layer, the wire-opposed region and the non-wire-opposed region each in a non-wire-forming region other than the wire-forming region of the first insulating layer.
    Type: Grant
    Filed: July 2, 2010
    Date of Patent: December 16, 2014
    Assignee: Rohm Co., Ltd.
    Inventors: Yuichi Nakao, Satoshi Kageyama, Masaru Naitou
  • Patent number: 8907389
    Abstract: The semiconductor device according to the present invention includes a ferroelectric film and an electrode stacked on the ferroelectric film. The electrode has a multilayer structure of an electrode lower layer in contact with the ferroelectric film and an electrode upper layer stacked on the electrode lower layer. The electrode upper layer is made of a conductive material having an etching selection ratio with respect to the materials for the ferroelectric film and the electrode lower layer. The upper surface of the electrode upper layer is planarized.
    Type: Grant
    Filed: September 25, 2009
    Date of Patent: December 9, 2014
    Assignee: Rohm Co., Ltd.
    Inventor: Yuichi Nakao
  • Publication number: 20140284731
    Abstract: A semiconductor device includes a substrate that is made of a semiconductor material and has a main surface formed with a recess. The semiconductor device also includes a wiring layer formed on the substrate, an electronic element housed in the recess, and a sealing resin covering at least a part of the electronic element.
    Type: Application
    Filed: March 25, 2014
    Publication date: September 25, 2014
    Applicant: ROHM CO., LTD.
    Inventors: Yuichi NAKAO, Yasuhiro FUWA
  • Publication number: 20140045308
    Abstract: A semiconductor storage device according to the present invention includes: a semiconductor substrate; an embedded insulator embedded in a trench formed in the semiconductor substrate and having an upper portion protruding above a top surface of the semiconductor substrate; a first insulating film formed on the top surface of the semiconductor substrate; a floating gate formed on the first insulating film at a side of the embedded insulator, having a side portion arching out above the embedded insulator, and having a side surface made of a flat surface and a curved surface continuing below the flat surface; a second insulating film contacting an upper surface, the flat surface and the curved surface of the floating gate; and a control gate opposing the upper surface, the flat surface and the curved surface of the floating gate across the second insulating film.
    Type: Application
    Filed: October 15, 2013
    Publication date: February 13, 2014
    Applicant: ROHM CO., LTD.
    Inventor: Yuichi NAKAO
  • Patent number: 8647984
    Abstract: The method of manufacturing a semiconductor device according to the present invention includes: an insulating layer forming step of forming an insulating layer made of an insulating material containing Si and O; a groove forming step of forming a groove in the insulating layer; a metal film applying step of covering the inner surface of the groove with a metal film made of MnOx (x: a number greater than zero) by sputtering; and a wire forming step of forming a Cu wire made of a metallic material mainly composed of Cu on the metal film.
    Type: Grant
    Filed: January 6, 2012
    Date of Patent: February 11, 2014
    Assignee: Rohm Co., Ltd.
    Inventors: Yuichi Nakao, Satoshi Kageyama
  • Publication number: 20130300001
    Abstract: The semiconductor device according to the present invention includes a semiconductor layer, an interlayer dielectric film formed on the semiconductor layer, a wire formed on the interlayer dielectric film with a metallic material to have a width of not more than 0.4 ?m, and a broad portion integrally formed on the wire to extend from the wire in the width direction thereof.
    Type: Application
    Filed: July 9, 2013
    Publication date: November 14, 2013
    Inventors: Satoshi KAGEYAMA, Yuichi NAKAO
  • Patent number: 8575676
    Abstract: A semiconductor storage device according to the present invention includes: a semiconductor substrate; an embedded insulator embedded in a trench formed in the semiconductor substrate and having an upper portion protruding above a top surface of the semiconductor substrate; a first insulating film formed on the top surface of the semiconductor substrate; a floating gate formed on the first insulating film at a side of the embedded insulator, having a side portion arching out above the embedded insulator, and having a side surface made of a flat surface and a curved surface continuing below the flat surface; a second insulating film contacting an upper surface, the flat surface and the curved surface of the floating gate; and a control gate opposing the upper surface, the flat surface and the curved surface of the floating gate across the second insulating film.
    Type: Grant
    Filed: September 29, 2009
    Date of Patent: November 5, 2013
    Assignee: Rohm Co., Ltd.
    Inventor: Yuichi Nakao
  • Patent number: 8508033
    Abstract: The semiconductor device according to the present invention includes a semiconductor layer, an interlayer dielectric film formed on the semiconductor layer, a wire formed on the interlayer dielectric film with a metallic material to have a width of not more than 0.4 ?m, and a broad portion integrally formed on the wire to extend from the wire in the width direction thereof.
    Type: Grant
    Filed: May 12, 2011
    Date of Patent: August 13, 2013
    Assignee: Rohm Co., Ltd.
    Inventors: Satoshi Kageyama, Yuichi Nakao
  • Publication number: 20130001785
    Abstract: A semiconductor device includes an interlayer insulating film, a wiring formed on the interlayer insulating film so as to protrude therefrom and made of a material having copper as a main component, and a passivation film formed so as to cover the wiring. The passivation film is made of a laminated film in which a first nitride film, an intermediate film, and a second nitride film are laminated in that order from the wiring side. The intermediate film is made of an insulating material (for example, an oxide) differing from those of the first and second nitride films.
    Type: Application
    Filed: April 1, 2011
    Publication date: January 3, 2013
    Inventors: Yuichi Nakao, Tadao Ohta
  • Publication number: 20120199942
    Abstract: A semiconductor device includes a lower wiring layer made of a conductive material; an upper wiring layer formed in an upper layer than the lower wiring layer; and a fuse film, at least a portion of the fuse film being formed in a plug formation layer in which a plug for connecting the lower wiring layer and the upper wiring layer is formed, and made of a conductive material including a metallic material other than copper.
    Type: Application
    Filed: February 7, 2012
    Publication date: August 9, 2012
    Applicant: ROHM CO., LTD.
    Inventors: Satoshi KAGEYAMA, Yuichi NAKAO
  • Publication number: 20120132984
    Abstract: A contact plug 40 electrically connected to an impurity diffusion region between sidewalls of an adjacent pair of memory cells 1 is provided to pass through an interlayer dielectric film 18. A side wall of a contact hole 41 is covered with a sealing film 42 denser than the interlayer dielectric film 18. The contact plug 40 includes a barrier metal film 43 formed to cover a surface of the sealing film 42 and a bottom surface portion of the contact hole 41 and a metal plug 44 embedded in the contact hole 41 in a state surrounded by the barrier metal film 43.
    Type: Application
    Filed: February 2, 2012
    Publication date: May 31, 2012
    Applicant: ROHM CO., LTD.
    Inventors: Michihiko Mifuji, Yuichi Nakao, Toshikazu Mizukoshi, Bungo Tanaka, Taku Shibaguchi, Gentaro Morikawa
  • Publication number: 20120108059
    Abstract: The method of manufacturing a semiconductor device according to the present invention includes: an insulating layer forming step of forming an insulating layer made of an insulating material containing Si and O; a groove forming step of forming a groove in the insulating layer; a metal film applying step of covering the inner surface of the groove with a metal film made of MnOx (x: a number greater than zero) by sputtering; and a wire forming step of forming a Cu wire made of a metallic material mainly composed of Cu on the metal film.
    Type: Application
    Filed: January 6, 2012
    Publication date: May 3, 2012
    Applicant: ROHM CO., LTD.
    Inventors: Yuichi NAKAO, Satoshi Kageyama
  • Patent number: 8164160
    Abstract: A semiconductor device according to the present invention has a multilayer wiring structure laminating and disposing a plurality of with sandwiching an insulating film and includes: a copper wire having copper as a main component; an insulating film formed on the copper wire; an aluminum wire having aluminum as a main component and formed on the insulating film to be electrically connected to the copper wire via a via hole formed to penetrate through the insulating film; and a surface protective film formed on the aluminum wire; and the surface protective film formed with a pad opening exposing a portion of the aluminum wire as an electrode pad for electrical connection with an external portion.
    Type: Grant
    Filed: May 30, 2008
    Date of Patent: April 24, 2012
    Assignee: Rohm Co., Ltd.
    Inventors: Yuichi Nakao, Takahisa Yamaha
  • Patent number: 8164197
    Abstract: A semiconductor device according to the present invention includes: a first interlayer dielectric film; a lower wire formed on the first interlayer dielectric film; a second interlayer dielectric film formed on the first interlayer dielectric film and the lower wire; and an upper wire formed on the second interlayer dielectric film to intersect with a prescribed portion of the lower wire in plan view. The first interlayer dielectric film is provided with a groove dug from the upper surface thereof in a region including the prescribed portion in plan view. The prescribed portion enters the groove. At least a portion of the second interlayer dielectric film formed on the lower wire has a planar upper surface.
    Type: Grant
    Filed: August 6, 2008
    Date of Patent: April 24, 2012
    Assignee: Rohm Co., Ltd.
    Inventors: Yuichi Nakao, Satoshi Kageyama
  • Patent number: 8125084
    Abstract: A semiconductor device according to the present invention includes: a semiconductor substrate; a first copper interconnection provided on the semiconductor substrate; an insulating layer provided over the first copper interconnection and having a hole extending therethrough to the first copper interconnection; a barrier layer composed of a tantalum-containing material and covering at least a sidewall of the hole and a part of the first copper interconnection exposed in the hole; and a second copper interconnection provided in intimate contact with the barrier layer and electrically connected to the first copper interconnection via the barrier layer; wherein the barrier layer has a nitrogen concentration profile such that the concentration of nitrogen contained in the material varies to be lower in a boundary portion of the barrier layer adjacent to the first copper interconnection and in a boundary portion of the barrier layer adjacent to the second copper interconnection and higher in an intermediate portion
    Type: Grant
    Filed: October 11, 2007
    Date of Patent: February 28, 2012
    Assignee: ROHM Co., Ltd.
    Inventors: Ryosuke Nakagawa, Takahisa Yamaha, Yuichi Nakao, Katsumi Sameshima, Satoshi Kageyama
  • Patent number: 8110504
    Abstract: The method of manufacturing a semiconductor device according to the present invention includes: an insulating layer forming step of forming an insulating layer made of an insulating material containing Si and O; a groove forming step of forming a groove in the insulating layer; a metal film applying step of covering the inner surface of the groove with a metal film made of MnOx (x: a number greater than zero) by sputtering; and a wire forming step of forming a Cu wire made of a metallic material mainly composed of Cu on the metal film.
    Type: Grant
    Filed: August 5, 2009
    Date of Patent: February 7, 2012
    Assignee: Rohm Co., Ltd.
    Inventors: Yuichi Nakao, Satoshi Kageyama
  • Publication number: 20120025302
    Abstract: A semiconductor device according to the present invention includes: a semiconductor layer made of silicon; a trench formed by digging in from a top surface of the semiconductor layer; a gate insulating film formed on an inner wall surface of the trench and made of silicon oxide; a gate electrode embedded in the trench via the gate insulating film and made of a polysilicon doped with an impurity; and an oxidation-resistant metal film disposed on a top surface of the gate electrode and covering the top surface.
    Type: Application
    Filed: October 6, 2011
    Publication date: February 2, 2012
    Applicant: ROHM CO., LTD.
    Inventor: Yuichi NAKAO
  • Patent number: 8102051
    Abstract: The semiconductor device according to the present invention includes a first insulating layer made of a material containing Si and O, a groove shaped by digging down the first insulating layer, an embedded body, embedded in the groove, made of a metallic material mainly composed of Cu, a second insulating layer, stacked on the first insulating layer and the embedded body, made of a material containing Si and O, and a barrier film, formed between the embedded body and each of the first insulating layer and the second insulating layer, made of MnxSiyOz (x, y and z: numbers greater than zero).
    Type: Grant
    Filed: June 20, 2008
    Date of Patent: January 24, 2012
    Assignee: Rohm Co., Ltd.
    Inventor: Yuichi Nakao
  • Patent number: 8058684
    Abstract: A semiconductor device according to the present invention includes: a semiconductor layer made of silicon; a trench formed by digging in from a top surface of the semiconductor layer; a gate insulating film formed on an inner wall surface of the trench and made of silicon oxide; a gate electrode embedded in the trench via the gate insulating film and made of a polysilicon doped with an impurity; and an oxidation-resistant metal film disposed on a top surface of the gate electrode and covering the top surface.
    Type: Grant
    Filed: September 12, 2008
    Date of Patent: November 15, 2011
    Assignee: Rohm Co., Ltd.
    Inventor: Yuichi Nakao
  • Patent number: 8044491
    Abstract: The semiconductor device according to the present invention includes a lower electrode made of a metallic material, a capacitance film made of an insulating material and laminated on the lower electrode, an upper electrode made of a metallic material, opposed to the lower electrode through the capacitance film, and having an outline smaller than that of the lower electrode in plan view along the opposed direction, and a protective film made of the same material as that of the capacitance film and laminated on the upper electrode.
    Type: Grant
    Filed: July 15, 2010
    Date of Patent: October 25, 2011
    Assignee: Rohm Co., Ltd.
    Inventors: Ryotaro Yagi, Yuichi Nakao, Isamu Nishimura