Patents by Inventor Yuichi Nakao

Yuichi Nakao has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20160268273
    Abstract: The semiconductor device according to the present invention includes a ferroelectric film and an electrode stacked on the ferroelectric film. The electrode has a multilayer structure of an electrode lower layer in contact with the ferroelectric film and an electrode upper layer stacked on the electrode lower layer. The electrode upper layer is made of a conductive material having an etching selection ratio with respect to the materials for the ferroelectric film and the electrode lower layer. The upper surface of the electrode upper layer is planarized.
    Type: Application
    Filed: May 25, 2016
    Publication date: September 15, 2016
    Applicant: ROHM CO., LTD.
    Inventor: Yuichi NAKAO
  • Publication number: 20160247810
    Abstract: A semiconductor storage device includes an insulating layer. A ferroelectric capacitor is on the insulating layer and includes a lower electrode, a ferroelectric film, and an upper electrode. An interlayer insulating film is formed on the insulating layer, and has an opening where the ferroelectric capacitor is disposed. A first metal plug is formed in the insulating layer and connected to the lower electrode via the opening. A second metal plug is embedded in the insulating layer outside the ferroelectric capacitor. A hydrogen barrier film covers the ferroelectric capacitor and the interlayer insulating film. An upper surface of the interlayer insulating film is higher than an upper surface of the first metal plug so that a step is therebetween. The lower electrode is formed on the upper surface of the interlayer insulating film, the upper surface of the first metal plug and the step.
    Type: Application
    Filed: May 4, 2016
    Publication date: August 25, 2016
    Applicant: ROHM CO., LTD.
    Inventor: Yuichi NAKAO
  • Patent number: 9425147
    Abstract: A semiconductor device includes an interlayer insulating film; a wiring formed on the interlayer insulating film so as to protrude there from and made of a material having copper as a main component, the wiring having a thickness direction and having a cross sectional shape of an inverted trapezoid that becomes wider in width with distance away from the interlayer insulating film; and a passivation film formed so as to cover the wiring. The passivation film is made of a laminated film in which a first nitride film, an intermediate film, and a second nitride film are laminated in that order from the wiring side. The intermediate film is made of an insulating material differing from those of the first and second nitride films, and has a tapered portion having a cross sectional shape of a trapezoid that becomes narrower in width with distance away from the interlayer insulating film.
    Type: Grant
    Filed: April 1, 2011
    Date of Patent: August 23, 2016
    Assignee: ROHM CO., LTD.
    Inventors: Yuichi Nakao, Tadao Ohta
  • Publication number: 20160229690
    Abstract: A semiconductor device includes a substrate that is made of a semiconductor material and has a main surface formed with a recess. The semiconductor device also includes a wiring layer formed on the substrate, an electronic element housed in the recess, and a sealing resin covering at least a part of the electronic element.
    Type: Application
    Filed: April 19, 2016
    Publication date: August 11, 2016
    Inventors: Yuichi NAKAO, Yasuhiro FUWA
  • Publication number: 20160225711
    Abstract: A semiconductor device includes a semiconductor substrate, a first insulating layer laminated on the semiconductor substrate, a first metal wiring pattern embedded in a wire-forming region of the first insulating layer, a second insulating layer laminated on the first insulating layer, a second metal wiring pattern embedded in a wire-forming region of the second insulating layer and first dummy metal patterns embedded each in a wire-opposed region opposing to the wire-forming region of the second insulating layer and in a non-wire-opposed region opposing to a non-wire-forming region other than the wire-forming region of the second insulating layer, the wire-opposed region and the non-wire-opposed region each in a non-wire-forming region other than the wire-forming region of the first insulating layer.
    Type: Application
    Filed: April 14, 2016
    Publication date: August 4, 2016
    Applicant: ROHM CO., LTD.
    Inventors: Yuichi NAKAO, Satoshi KAGEYAMA, Masaru NAITOU
  • Patent number: 9406684
    Abstract: The semiconductor device according to the present invention includes a ferroelectric film and an electrode stacked on the ferroelectric film. The electrode has a multilayer structure of an electrode lower layer in contact with the ferroelectric film and an electrode upper layer stacked on the electrode lower layer. The electrode upper layer is made of a conductive material having an etching selection ratio with respect to the materials for the ferroelectric film and the electrode lower layer. The upper surface of the electrode upper layer is planarized.
    Type: Grant
    Filed: October 17, 2014
    Date of Patent: August 2, 2016
    Assignee: ROHM CO., LTD.
    Inventor: Yuichi Nakao
  • Patent number: 9362294
    Abstract: The semiconductor device according to the present invention includes a ferroelectric film and an electrode stacked on the ferroelectric film. The electrode has a multilayer structure of an electrode lower layer in contact with the ferroelectric film and an electrode upper layer stacked on the electrode lower layer. The electrode upper layer is made of a conductive material having an etching selection ratio with respect to the materials for the ferroelectric film and the electrode lower layer. The upper surface of the electrode upper layer is planarized.
    Type: Grant
    Filed: October 17, 2014
    Date of Patent: June 7, 2016
    Assignee: ROHM CO., LTD.
    Inventor: Yuichi Nakao
  • Patent number: 9362295
    Abstract: A semiconductor-storage-device manufacturing method of the present invention is a method for manufacturing a semiconductor storage device provided with a ferroelectric capacitor including a lower electrode, a ferroelectric film, and an upper electrode, and the method includes a step of embedding a first metal plug and a second metal plug in an insulating layer; a step of forming a covering layer that covers at least the second metal plug while securing a part that comes into electric contact with the first metal plug; a step of forming a deposit structure by sequentially depositing a material for the lower electrode, a material for the ferroelectric film, and a material for the upper electrode after forming the covering layer; and a step of forming the ferroelectric capacitor by etching and removing other parts except a part of the deposit structure such that the part of the deposit structure remains on the first metal plug.
    Type: Grant
    Filed: February 6, 2015
    Date of Patent: June 7, 2016
    Assignee: ROHM CO., LTD.
    Inventor: Yuichi Nakao
  • Patent number: 9337090
    Abstract: The semiconductor device according to the present invention includes a semiconductor substrate, a first insulating layer laminated on the semiconductor substrate, a first metal wiring pattern embedded in a wire-forming region of the first insulating layer, a second insulating layer laminated on the first insulating layer, a second metal wiring pattern embedded in a wire-forming region of the second insulating layer and first dummy metal patterns embedded each in a wire-opposed region opposing to the wire-forming region of the second insulating layer and in a non-wire-opposed region opposing to a non-wire-forming region other than the wire-forming region of the second insulating layer, the wire-opposed region and the non-wire-opposed region each in a non-wire-forming region other than the wire-forming region of the first insulating layer.
    Type: Grant
    Filed: October 6, 2015
    Date of Patent: May 10, 2016
    Assignee: ROHM CO., LTD.
    Inventors: Yuichi Nakao, Satoshi Kageyama, Masaru Naitou
  • Patent number: 9331006
    Abstract: A semiconductor device includes a substrate that is made of a semiconductor material and has a main surface formed with a recess. The semiconductor device also includes a wiring layer formed on the substrate, an electronic element housed in the recess, and a sealing resin covering at least a part of the electronic element.
    Type: Grant
    Filed: March 25, 2014
    Date of Patent: May 3, 2016
    Assignee: ROHM CO., LTD.
    Inventors: Yuichi Nakao, Yasuhiro Fuwa
  • Publication number: 20160027690
    Abstract: The semiconductor device according to the present invention includes a semiconductor substrate, a first insulating layer laminated on the semiconductor substrate, a first metal wiring pattern embedded in a wire-forming region of the first insulating layer, a second insulating layer laminated on the first insulating layer, a second metal wiring pattern embedded in a wire-forming region of the second insulating layer and first dummy metal patterns embedded each in a wire-opposed region opposing to the wire-forming region of the second insulating layer and in a non-wire-opposed region opposing to a non-wire-forming region other than the wire-forming region of the second insulating layer, the wire-opposed region and the non-wire-opposed region each in a non-wire-forming region other than the wire-forming region of the first insulating layer.
    Type: Application
    Filed: October 6, 2015
    Publication date: January 28, 2016
    Applicant: ROHM CO., LTD.
    Inventors: Yuichi NAKAO, Satoshi KAGEYAMA, Masaru NAITOU
  • Patent number: 9184132
    Abstract: The semiconductor device according to the present invention includes a semiconductor substrate, a first insulating layer laminated on the semiconductor substrate, a first metal wiring pattern embedded in a wire-forming region of the first insulating layer, a second insulating layer laminated on the first insulating layer, a second metal wiring pattern embedded in a wire-forming region of the second insulating layer and first dummy metal patterns embedded each in a wire-opposed region opposing to the wire-forming region of the second insulating layer and in a non-wire-opposed region opposing to a non-wire-forming region other than the wire-forming region of the second insulating layer, the wire-opposed region and the non-wire-opposed region each in a non-wire-forming region other than the wire-forming region of the first insulating layer.
    Type: Grant
    Filed: November 6, 2014
    Date of Patent: November 10, 2015
    Assignee: ROHM CO., LTD.
    Inventors: Yuichi Nakao, Satoshi Kageyama, Masaru Naitou
  • Publication number: 20150287678
    Abstract: A semiconductor device includes a lower wiring layer made of a conductive material; an upper wiring layer formed in an upper layer than the lower wiring layer; and a fuse film, at least a portion of the fuse film being formed in a plug formation layer in which a plug for connecting the lower wiring layer and the upper wiring layer is formed, and made of a conductive material including a metallic material other than copper.
    Type: Application
    Filed: June 18, 2015
    Publication date: October 8, 2015
    Applicant: ROHM CO., LTD.
    Inventors: Satoshi KAGEYAMA, Yuichi NAKAO
  • Publication number: 20150253121
    Abstract: A semiconductor device is provided with a substrate made of a semiconductor material, an interconnect layer, at least one electronic element, and a sealing resin. The substrate has a main surface and a pair of lateral surfaces that are orthogonal to the main surface and face in opposite directions to each other. A recessed portion that is recessed from the main surface and has an opening portion that opens on at least one of the pair of lateral surfaces is formed in the substrate. The interconnect layer is formed on the substrate. The electronic element is an orientation sensor, for example, and is accommodated in the recessed portion of the substrate. The sealing resin covers the electronic element.
    Type: Application
    Filed: March 5, 2015
    Publication date: September 10, 2015
    Inventors: Yuichi NAKAO, Yasuhiro FUWA
  • Patent number: 9082769
    Abstract: A semiconductor device includes a lower wiring layer made of a conductive material; an upper wiring layer formed in an upper layer than the lower wiring layer; and a fuse film, at least a portion of the fuse film being formed in a plug formation layer in which a plug for connecting the lower wiring layer and the upper wiring layer is formed, and made of a conductive material including a metallic material other than copper.
    Type: Grant
    Filed: February 7, 2012
    Date of Patent: July 14, 2015
    Assignee: ROHM CO., LTD.
    Inventors: Satoshi Kageyama, Yuichi Nakao
  • Publication number: 20150155288
    Abstract: A semiconductor-storage-device manufacturing method of the present invention is a method for manufacturing a semiconductor storage device provided with a ferroelectric capacitor including a lower electrode, a ferroelectric film, and an upper electrode, and the method includes a step of embedding a first metal plug and a second metal plug in an insulating layer; a step of forming a covering layer that covers at least the second metal plug while securing a part that comes into electric contact with the first metal plug; a step of forming a deposit structure by sequentially depositing a material for the lower electrode, a material for the ferroelectric film, and a material for the upper electrode after forming the covering layer; and a step of forming the ferroelectric capacitor by etching and removing other parts except a part of the deposit structure such that the part of the deposit structure remains on the first metal plug.
    Type: Application
    Filed: February 6, 2015
    Publication date: June 4, 2015
    Inventor: Yuichi NAKAO
  • Patent number: 8981440
    Abstract: A semiconductor-storage-device manufacturing method of the present invention is a method for manufacturing a semiconductor storage device provided with a ferroelectric capacitor including a lower electrode, a ferroelectric film, and an upper electrode, and the method includes a step of embedding a first metal plug and a second metal plug in an insulating layer; a step of forming a covering layer that covers at least the second metal plug while securing apart that comes into electric contact with the first metal plug; a step of forming a deposit structure by sequentially depositing a material for the lower electrode, a material for the ferroelectric film, and a material for the upper electrode after forming the covering layer; and a step of forming the ferroelectric capacitor by etching and removing other parts except a part of the deposit structure such that the part of the deposit structure remains on the first metal plug.
    Type: Grant
    Filed: September 16, 2009
    Date of Patent: March 17, 2015
    Assignee: Rohm Co., Ltd.
    Inventor: Yuichi Nakao
  • Publication number: 20150061145
    Abstract: The semiconductor device according to the present invention includes a semiconductor substrate, a first insulating layer laminated on the semiconductor substrate, a first metal wiring pattern embedded in a wire-forming region of the first insulating layer, a second insulating layer laminated on the first insulating layer, a second metal wiring pattern embedded in a wire-forming region of the second insulating layer and first dummy metal patterns embedded each in a wire-opposed region opposing to the wire-forming region of the second insulating layer and in a non-wire-opposed region opposing to a non-wire-forming region other than the wire-forming region of the second insulating layer, the wire-opposed region and the non-wire-opposed region each in a non-wire-forming region other than the wire-forming region of the first insulating layer.
    Type: Application
    Filed: November 6, 2014
    Publication date: March 5, 2015
    Applicant: ROHM CO., LTD.
    Inventors: Yuichi NAKAO, Satoshi KAGEYAMA, Masaru NAITOU
  • Publication number: 20150054128
    Abstract: The semiconductor device according to the present invention includes a ferroelectric film and an electrode stacked on the ferroelectric film. The electrode has a multilayer structure of an electrode lower layer in contact with the ferroelectric film and an electrode upper layer stacked on the electrode lower layer. The electrode upper layer is made of a conductive material having an etching selection ratio with respect to the materials for the ferroelectric film and the electrode lower layer. The upper surface of the electrode upper layer is planarized.
    Type: Application
    Filed: October 17, 2014
    Publication date: February 26, 2015
    Applicant: ROHM CO., LTD.
    Inventor: Yuichi NAKAO
  • Publication number: 20150035118
    Abstract: The semiconductor device according to the present invention includes a ferroelectric film and an electrode stacked on the ferroelectric film. The electrode has a multilayer structure of an electrode lower layer in contact with the ferroelectric film and an electrode upper layer stacked on the electrode lower layer. The electrode upper layer is made of a conductive material having an etching selection ratio with respect to the materials for the ferroelectric film and the electrode lower layer. The upper surface of the electrode upper layer is planarized.
    Type: Application
    Filed: October 17, 2014
    Publication date: February 5, 2015
    Applicant: ROHM CO., LTD.
    Inventor: Yuichi NAKAO