Abstract: Two flow tubes 1 and 2 of a Coriolis mass flow meter are formed into an arch shape, with the tubes bent in only one direction. Entry-side and exit-side manifolds 25 are smoothly bent from the inlet of the entry-side manifold and the outlet of the exit-side manifold to joints connecting the two flow tubes to the manifolds, and connected to the flow tubes 1 and 2 at the joints at a predetermined angle in the same direction. By making the flow tubes into a parallel arched tube structure having good stress distribution and shock resistance, effects on the flow meter of external oscillations, installation conditions, piping stresses and thermal stresses can be reduced.

Abstract: Each of two flow tubes assumes an arcuate shape consisting of a central arcuate segment and two linear segments located on opposite sides of the central arcuate segment. The inside diameter of the flow tubes and the linear distance between end points of each of the flow tubes are determined on the basis of a target pressure loss arising from passage of a fluid to be measured through a manifold and the flow tube at the maximum flow rate, a target time phase difference between sine wave outputs from vibration sensors at the maximum flow rate, and a target natural frequency of the flow tubes. The length of the linear segments is selected so as to reduce thermal stress induced from an abrupt change in the temperature of the fluid to be measured, and the shape of the flow tubes is determined so as to reduce the vertical height of the flow tubes, so long as the thermal stress is substantially constant even when the length of the linear segments is varied.

Abstract: Each of two flow tubes assumes an arcuate shape consisting of a central arcuate segment and two linear segments located on opposite sides of the central arcuate segment. The inside diameter of the flow tubes and the linear distance between end points of each of the flow tubes are determined on the basis of a target pressure loss arising from passage of a fluid to be measured through a manifold and the flow tube at the maximum flow rate, a target time phase difference between sine wave outputs from vibration sensors at the maximum flow rate, and a target natural frequency of the flow tubes. The length of the linear segments is selected so as to reduce thermal stress induced from an abrupt change in the temperature of the fluid to be measured, and the shape of the flow tubes is determined so as to reduce the vertical height of the flow tubes, so long as the thermal stress is substantially constant even when the length of the linear segments is varied.

Abstract: A Coriolis mass flowmeter of a type in which a fluid to be measured is caused to flow in series by forming two parallel flow tubes 1 and 2, which are obtained by bending one conduit. The inlet portion of conduit between an external connecting portion 35 connected to inlet piping and the inlet of one flow tube 2 is bent in the shape of the letter L and bent in another direction in combination, and the outlet portion of conduit between an external connecting portion 36 connected to outlet piping and the outlet of the other flow tube 1 is bent in the shape of the letter L symmetrically with respect to the above inlet portion of conduit and bent in another direction in combination. The external connecting portions 35 and 36 are arranged on the same axis. The present invention simplifies the construction of connection to external piping, simplifies the assembling of the Coriolis mass flowmeter itself, and permits a high-accuracy measurement of mass flow rate by reducing the vibrations of external piping, etc.

Abstract: On the surface of a semiconductor substrate between a source region and a drain region formed on the semiconductor substrate, an insulating layer, a conductive thin film used as a floating electrode, a ferroelectric thin film and a conductive thin film used as a control electrode are successively formed. Writing or erasing is performed by causing a potential difference between the control electrode and the semiconductor substrate to reverse the polarization of the ferroelectric thin film.

Abstract: An external bus I/F section has a function in which, when a bus access is requested by an instruction execution section, high-order several bits of a logical address generated by a CPU are outputted from an output terminal to the outside of a chip, as a space identifier for indicating which of an integrated ROM space, an integrated RAM space, and the external space is accessed by a currently executed program. A part of an address generated by the CPU is used so that the space which is accessed by the currently executed program is known from the outside in real time without requiring an external hardware.

Abstract: An electrophotographic printer includes: a photosensitive drum; a latent image forming portion for forming electrostatic latent images on the photosensitive drum based on print information; a developing portion for developing the electrostatic latent images using toner; an intermediate transfer drum for receiving the toner images from the photosensitive drum; a transportation portion for delivering a recording medium; and a transfer roll for transferring the toner image from the intermediate transfer roll to the recording medium. A pressure force P.sub.1 between the photosensitive drum and the intermediate transfer drum is less than a pressure force P.sub.2 between the transfer roll and the intermediate transfer drum. P.sub.1 and P.sub.2 may also have the relationship P.sub.1 .gtoreq.P.sub.2 sin.theta., where .theta.

Abstract: On the surface of a semiconductor substrate between a source region and a drain region formed on the semiconductor substrate, an insulating layer, a conductive thin film used as a floating electrode, a ferroelectric thin film and a conductive thin film used as a control electrode are successively formed. Writing or erasing is performed by causing a potential difference between the control electrode and the semiconductor substrate to reverse the polarization of the ferroelectric thin film.

Abstract: The present invention is a printing apparatus, in which toner images on a latent image bearing member are electrically transferred onto an intermediate transfer member, for recording onto a recording medium, comprising charging the surface of the intermediate transfer member in the same polarity as the toner image whenever each of the toner images is transferred from the latent image bearing member onto the intermediate transfer member.The present invention can present a printing apparatus and printing method for suppressing the reverse transfer of the toner images onto the photosensitive element when the toner images are transferred in lamination onto the intermediate transfer member, for example, in an electrophotographic printer.

Abstract: An oscillation stop signal holding latch 3 which stores a value deciding significant/unsignificant of an oscillation stop signal 4, and a NOR gate 21 which controls, when the oscillation stop signal 4 is significant, to stop the generation of a clock signal 7 and controls, when a predetermined signal is inputted from an input terminal 1 of an external signal in the abovementioned states with the oscillation stop signal being unsignificant, to resume the generation of the clock signal 7, and further a sampling circuit 10 between the input terminal 1 of the external signal and the oscillation stop signal holding latch 3 are provided. And a gate circuit 30 which forcibly makes the oscillation stop signal 4 become unsignificant so as to generate the clock signal 7 when the input signal from the input terminal 1 of the external signal is significant is provided. This enables the sampling circuit 10 to sample the input signal from the input terminal 1 of the external signal.

Abstract: A digital circuit apparatus having an A/D converter for digitalizing a control voltage which determines the oscillation frequency of an internal clock outputted from a voltage-controlled oscillator, a storing unit for holding a digitalized value, a D/A converter with corrective function for correcting the digital value being held and subjecting the corrected digital value to D/A conversion, and a lock detector for detecting the matching in phase of the internal clock and an external clock. Phase information obtained when the internal clock and the external clock match in phase is held so that, when the generation of the internal clock outputted from the voltage-controlled oscillator is halted and then resumed, the matching in phase of the external clock and internal clock can be achieved in a short period of time.

Abstract: A bus controller (20) for a data processing system, in which data is transferred between a bus master (10) and a bus slave (30) of a plurality of different data port sizes, is able to obtain port size information from an address signal using an incorporated address area/port size correspondence table (211), whereby a port size signal as a response signal from the bus slave is made unnecessary, thus simplifying the data processing system.

Abstract: A multiplying circuit having sign carry correcting circuits which set all bits of a multiplier Y subjected to sign extension to a certain specific value ("0" or "1"), and when a sign bit, which is the highest bit of effective data in the data to be multiplied, is carried, a specific value signal is input to a bit input portion of a Booth decoder, receiving both the least significant invalid bit and the most significant effective bit of the multiplier, according to a value of a sign extension control signal. In addition, a value inputted to partial product adding circuits from an intermediate result shift circuit is set to a multiplicand value according to the value of a predetermined number of least significant bits of the multiplier, and the multiplier bits excluding the predetermined number of least significant bits inputted to the intermediate result shift circuit are inputted to multiple generating circuits.

Abstract: A data processor includes an interrupt control unit (102); a direct memory access control unit (103); a selection unit (104) for selecting a connection of ready and error signals from a serial communication control unit and external interrupt and DMA request signals with interrupt inputs to the interrupt and the DMA control units; and a selection setting unit (105) for setting a selection mode of the selection unit, thereby making possible to not only switch between a process by interrupt and a process by DMA transfer by programming according to the application but also make efficient use of the hardware resources in the data processor.

Abstract: An electrophotographic printer method for a printer including a photosensitive drum; a latent image former for forming electrostatic latent images based on the color-separated print information for individual colors on the photosensitive drum; a wet developer for developing the electrostatic latent images successively into toner images for the individual colors using liquid toners of different colors corresponding to the print information and for squeezing surplus liquid toners on the photosensitive drum; an intermediate transfer drum so that the toner images of the individual colors developed on the photosensitive drum are successively transferred to and deposited in layers to form a multicolor toner image; a transportation device for delivering a recording medium; and a transfer-fixing device for transferring to and fixing the multicolor toner image on the recording medium.

Abstract: A vortex flow meter capable of operating with minimum piping effect is disclosed. A stream-lined protrusion , extending toward the upstream side is disposed at the upstream surface 2 of a vortex generator joined to the inner wall 1 of a flow pipe in order to remove thereat horseshoe vortexes produced in front of the vortex generator. Therefore, the possible affection of horseshoe vortexes, that may considerably depend upon the piping conditions, can be eliminated.

Abstract: A wait control device according to the present invention instructs a central processing unit (CPU) to wait for the start of its operation until the device receives a process completion signal from a memory unit or an I/O unit, and comprises setting means for setting the time of said CPU to wait for the start of its operation in the memory unit or the I/O unit accessed by the CPU, judgement means for judging system operation to be time out error when no process completion signal is presented during said time of the CPU, and selector means for selecting whether it passes a signal concerning the judgement of the time out error or successively waits for said processing completion signal.

Abstract: A bus controller (20) for a data processing system, in which data is transferred between a bus master (10) and a bus slave (30) of a plurality of different data port sizes, is able to obtain port size information from an address signal using an incorporated address area/port size correspondence table (211), whereby a port size signal as a response signal from the bus slave is made unnecessary, thus simplifying the data processing system.

Abstract: A method is provided for decreasing the power consumption of a sequential digital circuit having a plurality of states being determined from the current state and the input conditions and entered upon the assertion of a pulse from one or more clocks. The method consists of interrupting the switching created by the clock pulses and maintaining the system in a quiescent state. It is first determined whether a subsequent clock pulse will lead to a change in the state of the circuit. If it will, the circuit either waits for a change in the input conditions and state of the circuit, or changes some of the input conditions, depending on the embodiment of the invention. When a circuit configuration is reached in which further clock pulses will not lead to a change in the state of the circuit, the clock signal(s) are replaced by continuously asserted signals. The feedback loop thus created maintains the current state of the circuit in the absence of a clock signal and prevents further switching in the circuit.

Abstract: A refresh control circuit for a processor which is connected to dynamic random access memory via an address bus, a data bus and control signal lines. A refresh control signal is output at predetermined intervals to refresh the dynamic random access memory. The refresh control circuit includes control circuitry and an address generator. The address generator latches a value received from the control circuitry. Based on such latched value, a refresh address is changed by the N-th power of 2, N corresponding to the number of memory banks of the dynamic random access memory.