Patents by Inventor Yuki Nakano

Yuki Nakano has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20220157606
    Abstract: A method for producing a semiconductor power device includes forming a gate trench from a surface of the semiconductor layer toward an inside thereof. A first insulation film is formed on the inner surface of the gate trench. The method also includes removing a part on a bottom surface of the gate trench in the first insulation film. A second insulation film having a dielectric constant higher than SiO2 is formed in such a way as to cover the bottom surface of the gate trench exposed by removing the first insulation film.
    Type: Application
    Filed: February 2, 2022
    Publication date: May 19, 2022
    Inventor: Yuki NAKANO
  • Publication number: 20220140095
    Abstract: A semiconductor device of the present invention includes a gate electrode buried in a gate trench of a first conductivity-type semiconductor layer, a first conductivity-type source region, a second conductivity-type channel region, and a first conductivity-type drain region formed in the semiconductor layer, a second trench selectively formed in a source portion defined in a manner containing the source region in the surface of the semiconductor layer, a trench buried portion buried in the second trench, a second conductivity-type channel contact region selectively disposed at a position higher than that of a bottom portion of the second trench in the source portion, and electrically connected with the channel region, and a surface metal layer disposed on the source portion, and electrically connected to the source region and the channel contact region.
    Type: Application
    Filed: November 23, 2021
    Publication date: May 5, 2022
    Inventor: Yuki NAKANO
  • Publication number: 20220140072
    Abstract: A semiconductor device of the present invention includes a semiconductor layer of a first conductivity type having a cell portion and an outer peripheral portion disposed around the cell portion, formed with a gate trench at a surface side of the cell portion, and a gate electrode buried in the gate trench via a gate insulating film, forming a channel at a portion lateral to the gate trench at ON-time, the outer peripheral portion has a semiconductor surface disposed at a depth position equal to or deeper than a depth of the gate trench, and the semiconductor device further includes a voltage resistant structure having a semiconductor region of a second conductivity type formed in the semiconductor surface of the outer peripheral portion.
    Type: Application
    Filed: January 13, 2022
    Publication date: May 5, 2022
    Inventors: Yuki NAKANO, Ryota NAKAMURA
  • Publication number: 20220130821
    Abstract: The semiconductor device of the present invention includes a semiconductor substrate, a switching element which is defined on the semiconductor substrate, and a temperature sense element which is provided on the surface of the semiconductor substrate independently from the switching element and characterized by being dependent on a temperature.
    Type: Application
    Filed: January 11, 2022
    Publication date: April 28, 2022
    Inventor: Yuki NAKANO
  • Patent number: 11296223
    Abstract: A semiconductor device includes a semiconductor layer of a first conductivity type. A well region that is a second conductivity type well region is formed on a surface layer portion of the semiconductor layer and has a channel region defined therein. A source region that is a first conductivity type source region is formed on a surface layer portion of the well region. A gate insulating film is formed on the semiconductor layer and has a multilayer structure. A gate electrode is opposed to the channel region of the well region where a channel is formed through the gate insulating film.
    Type: Grant
    Filed: September 1, 2021
    Date of Patent: April 5, 2022
    Assignee: ROHM CO., LTD.
    Inventors: Shuhei Mitani, Yuki Nakano, Heiji Watanabe, Takayoshi Shimura, Takuji Hosoi, Takashi Kirino
  • Patent number: 11276574
    Abstract: A method for producing a semiconductor power device includes forming a gate trench from a surface of the semiconductor layer toward an inside thereof. A first insulation film is formed on the inner surface of the gate trench. The method also includes removing a part on a bottom surface of the gate trench in the first insulation film. A second insulation film having a dielectric constant higher than SiO2 is formed in such a way as to cover the bottom surface of the gate trench exposed by removing the first insulation film.
    Type: Grant
    Filed: October 13, 2020
    Date of Patent: March 15, 2022
    Assignee: ROHM CO., LTD.
    Inventor: Yuki Nakano
  • Publication number: 20220069088
    Abstract: An SiC semiconductor device includes an SiC semiconductor layer of a first conductivity type having a main surface, a source trench formed in the main surface and having a side wall and a bottom wall, a source electrode embedded in the source trench and having a side wall contact portion in contact with a region of the side wall of the source trench at an opening side of the source trench, a body region of a second conductivity type formed in a region of a surface layer portion of the main surface along the source trench, and a source region of the first conductivity type electrically connected to the side wall contact portion of the source electrode in a surface layer portion of the body region.
    Type: Application
    Filed: May 21, 2020
    Publication date: March 3, 2022
    Inventors: Yuki NAKANO, Kenji YAMAMOTO, Seigo MORI
  • Publication number: 20220069232
    Abstract: An organic electroluminescence device comprising: a cathode, an anode, and an organic layer disposed between the cathode and the anode, wherein the organic layer comprises an emitting layer and an electron barrier layer, the electron barrier layer is disposed between the anode and the emitting layer and is directly adjacent to the emitting layer, the emitting layer comprises a first compound represented by any one of the specific formulas (21), (41), and (51), and the electron barrier layer comprises a second compound which satisfies the following expression (M1): Ip(HT)?5.67 eV??(M1) wherein in the expression (M1), Ip(HT) is the ionization potential of the second compound.
    Type: Application
    Filed: November 7, 2019
    Publication date: March 3, 2022
    Applicant: IDEMITSU KOSAN CO.,LTD.
    Inventors: Tasuku HAKETA, Masatoshi SAITO, Yuki NAKANO, Satomi TASAKI, Kazuki NISHIMURA
  • Publication number: 20220059775
    Abstract: An organic electroluminescence device comprising: a cathode; an anode; and an organic layer disposed between the cathode and the anode, wherein the organic layer includes an emitting layer and a first layer; the first layer is disposed between the cathode and the emitting layer; the emitting layer contains a compound represented by the following formula (A1); and the first layer contains a compound represented by the following formula (B1).
    Type: Application
    Filed: June 14, 2019
    Publication date: February 24, 2022
    Applicant: IDEMITSU KOSAN CO.,LTD.
    Inventors: Yuki NAKANO, Satomi TASAKI, Kazuki NISHIMURA, Tomoki KATO
  • Patent number: 11257901
    Abstract: A semiconductor device of the present invention includes a semiconductor layer of a first conductivity type having a cell portion and an outer peripheral portion disposed around the cell portion, formed with a gate trench at a surface side of the cell portion, and a gate electrode buried in the gate trench via a gate insulating film, forming a channel at a portion lateral to the gate trench at ON-time, the outer peripheral portion has a semiconductor surface disposed at a depth position equal to or deeper than a depth of the gate trench, and the semiconductor device further includes a voltage resistant structure having a semiconductor region of a second conductivity type formed in the semiconductor surface of the outer peripheral portion.
    Type: Grant
    Filed: September 9, 2020
    Date of Patent: February 22, 2022
    Assignee: ROHM CO., LTD.
    Inventors: Yuki Nakano, Ryota Nakamura
  • Patent number: 11257812
    Abstract: The semiconductor device of the present invention includes a semiconductor substrate, a switching element which is defined on the semiconductor substrate, and a temperature sense element which is provided on the surface of the semiconductor substrate independently from the switching element and characterized by being dependent on a temperature.
    Type: Grant
    Filed: December 20, 2018
    Date of Patent: February 22, 2022
    Assignee: ROHM CO., LTD.
    Inventor: Yuki Nakano
  • Publication number: 20220052177
    Abstract: A semiconductor device of the present invention includes a semiconductor layer, a gate trench that defines a source region of a first conductivity type in the semiconductor layer, a channel region of a second conductivity type of a lower part of the source region, a source trench that passes through the source region and the channel region, an impurity region of the second conductivity type of a bottom part and a side part of the source trench, a source electrode on the semiconductor layer, and a highly-concentrated impurity region of the second conductivity type, the highly-concentrated impurity region having a contact portion connected to the source electrode at a surface of the semiconductor layer, the highly-concentrated impurity region passing through the source region and extending to a position deeper than the source region, the highly-concentrated impurity region having a concentration higher than the impurity region.
    Type: Application
    Filed: October 27, 2021
    Publication date: February 17, 2022
    Inventors: Yuki NAKANO, Ryota NAKAMURA
  • Publication number: 20220029099
    Abstract: A compound represented by the following formula (1), provided that at least one of R1 to R8 is a deuterium atom; and at least one of Ar1 and Ar2 is a substituted or unsubstituted fused aryl group in which only four or more benzene rings are fused.
    Type: Application
    Filed: November 8, 2019
    Publication date: January 27, 2022
    Applicant: IDEMITSU KOSAN CO.,LTD.
    Inventors: Taro YAMAKI, Satomi TASAKI, Hiroaki ITOI, Yuki NAKANO
  • Publication number: 20220020925
    Abstract: A compound represented by the following formula (1), wherein one or more pairs among R12 and R13, R13 and R14, R14 and R15, R16 and R17, R17 and R18, and R18 and R19 independently form a ring represented by the following formula (2A) or a ring represented by the following formula (2B), or do not form a ring represented by the following formula (2A) and do not form a ring represented by the following formula (2B); and one of R12 to R28 is bonded with L2.
    Type: Application
    Filed: September 7, 2021
    Publication date: January 20, 2022
    Applicant: IDEMITSU KOSAN CO.,LTD.
    Inventors: Yuki NAKANO, Ryota TAKAHASHI, Keita SEDA, Tomoki KATO, Hidetsugu IKEDA, Thomas SCHAEFER, Peter MURER, Carsten ROTHE
  • Patent number: 11217674
    Abstract: A semiconductor device of the present invention includes a gate electrode buried in a gate trench of a first conductivity-type semiconductor layer, a first conductivity-type source region, a second conductivity-type channel region, and a first conductivity-type drain region formed in the semiconductor layer, a second trench selectively formed in a source portion defined in a manner containing the source region in the surface of the semiconductor layer, a trench buried portion buried in the second trench, a second conductivity-type channel contact region selectively disposed at a position higher than that of a bottom portion of the second trench in the source portion, and electrically connected with the channel region, and a surface metal layer disposed on the source portion, and electrically connected to the source region and the channel contact region.
    Type: Grant
    Filed: January 23, 2020
    Date of Patent: January 4, 2022
    Assignee: ROHM CO., LTD.
    Inventor: Yuki Nakano
  • Publication number: 20210395233
    Abstract: A compound having a structure represented by the following formulas (a) and (b): wherein, in the formulas (a) and (b), a ring A, a ring B, a ring C and a ring D are independently a substituted or unsubstituted aromatic hydrocarbon ring having 6 to 50 ring carbon atoms, or a substituted or unsubstituted heterocyclic ring having 5 to 50 ring atoms; two or more of the ring A, the ring B, the ring C and the ring D are a heterocyclic ring; and each of sites *a, *b, *c and *d in the formula (a) and the formula (b) represents a position of an atom, and the atoms located in the sites *a, *b, *c and *d form one substituted or unsubstituted and saturated or unsaturated six-membered ring including four atoms thereof.
    Type: Application
    Filed: September 26, 2019
    Publication date: December 23, 2021
    Applicant: IDEMITSU KOSAN CO.,LTD.
    Inventors: Ryota TAKAHASHI, Hidetsugu IKEDA, Yuki NAKANO, Keita SEDA
  • Publication number: 20210399130
    Abstract: A semiconductor device includes a semiconductor layer of a first conductivity type. A well region that is a second conductivity type well region is formed on a surface layer portion of the semiconductor layer and has a channel region defined therein. A source region that is a first conductivity type source region is formed on a surface layer portion of the well region. A gate insulating film is formed on the semiconductor layer and has a multilayer structure. A gate electrode is opposed to the channel region of the well region where a channel is formed through the gate insulating film.
    Type: Application
    Filed: September 1, 2021
    Publication date: December 23, 2021
    Inventors: Shuhei MITANI, Yuki NAKANO, Heiji WATANABE, Takayoshi SHIMURA, Takuji HOSOI, Takashi KIRINO
  • Publication number: 20210399088
    Abstract: A semiconductor device includes a semiconductor layer made of a wide bandgap semiconductor and including a gate trench; a gate insulating film formed on the gate trench; and a gate electrode embedded in the gate trench to be opposed to the semiconductor layer through the gate insulating film. The semiconductor layer includes a first conductivity type source region; a second conductivity type body region; a first conductivity type drift region; a second conductivity type first breakdown voltage holding region; a source trench passing through the first conductivity type source region and the second conductivity type body region from the front surface and reaching a drain region; and a second conductivity type second breakdown voltage region selectively formed on an edge portion of the source trench where the sidewall and the bottom wall thereof intersect with each other in a parallel region of the source trench.
    Type: Application
    Filed: September 1, 2021
    Publication date: December 23, 2021
    Inventors: Yuki NAKANO, Ryota NAKAMURA
  • Publication number: 20210384347
    Abstract: A semiconductor device (A1) includes a semiconductor layer having a first face with a trench (3) formed thereon and a second face opposite to the first face, a gate electrode (41), and a gate insulating layer (5). The semiconductor layer includes a first n-type semiconductor layer (11), a second n-type semiconductor layer (12), a p-type semiconductor layer (13), and an n-type semiconductor region (14). The trench (3) is formed so as to penetrate through the p-type semiconductor layer (13) and to reach the second n-type semiconductor layer (12). The p-type semiconductor layer (13) includes an extended portion extending to a position closer to the second face of the semiconductor layer than the trench (3) is. Such structure allows suppressing dielectric breakdown in the gate insulating layer (5).
    Type: Application
    Filed: August 24, 2021
    Publication date: December 9, 2021
    Inventor: Yuki NAKANO
  • Publication number: 20210384348
    Abstract: A semiconductor device includes a semiconductor layer made of SiC. A transistor element having an impurity region is formed in a front surface portion of the semiconductor layer. A first contact wiring is formed on a back surface portion of the semiconductor layer, and defines one electrode electrically connected to the transistor element. The first contact wiring has a first wiring layer forming an ohmic contact with the semiconductor layer without a silicide contact and a second wiring layer formed on the first wiring layer and having a resistivity lower than that of the first wiring layer.
    Type: Application
    Filed: August 25, 2021
    Publication date: December 9, 2021
    Inventors: Yuki NAKANO, Ryota NAKAMURA