Abstract: An analysis device includes at least one processor, and memory storing instructions that, when executed by the at least one processor, cause the analysis device to, based on electron density patterns of a plurality of adjacent layers matching each other in orthogonal mesh data of a plurality of first layers divided in a first direction, fuse the plurality of adjacent layers into a fused layer and determine layer information about the fused layer, and based on the layer information about the fused layer, determine a scattering intensity distribution of X-rays incident in the first direction on a target structure that is represented by the orthogonal mesh data.

Abstract: An analysis device, an analysis method, and a computer program product that are configured to reduce an amount of time required to analyze scattering intensity distribution of X-rays are provided. An analysis device according to example embodiments includes an extraction circuit configured to extract information about an electron density difference at a different material interface included in a target structure and information about a surface element included at the different material interface from data representing the target structure, and a calculation circuit configured to calculate a surface integral at the different material interface based on the information about the electron density difference and the information about the surface element, and to calculate a scattering intensity distribution of X-rays irradiated to the target structure based on the surface integral.

Abstract: An example interpretation device includes an extraction circuit and a calculation circuit. The extraction circuit is configured to extract, from mesh data representing a target structure, parameters of each primitive structure that consists of a plurality of meshes corresponding to the same electron density. The calculation circuit is configured to calculate an analytical solution for a scattering intensity distribution of X-rays irradiated to each primitive structure based on the parameters of each primitive structure, and to calculate a scattering intensity distribution of the X-rays irradiated to the target structure based on the parameters of each primitive structure.

Abstract: A simulation method of a semiconductor process includes receiving first input data including values of a plurality of parameters received from the outside, setting a simulation using the plurality of parameters, improving the simulation by ordering the plurality of parameters, and executing the simulation by processing a job stored in a queue, wherein the optimizing includes generating a table with respect to the plurality of parameters, ordering the plurality of parameters based on the first input data, generating a job tree based on the plurality of ordered parameters, reconstructing the table based on the job tree, and generating the queue by storing the job in the queue based on the reconstructed table.

Abstract: A numerical information generating apparatus receives information of a programmable logic integrated circuit that includes a plurality of crossbar switches each including resistance change elements, calculates, for each of the plurality of crossbar switches, a base delay that is a delay in which influence of a load capacitance of other crossbar switch is excluded and a correction delay that is a delay caused by influence of a fanout of other crossbar switch, and further calculates a delay of each of the plurality of crossbar switches based on the base delay and the correction delay corresponding to each of the plurality of crossbar switches.

Abstract: In order to eliminate an increase in the source potential of a transistor selected during writing or reading, this semiconductor device is equipped with: a variable-resistance type first switch having a first terminal and a second terminal; a variable-resistance type second switch having a third terminal and a fourth terminal, the third terminal being connected to the second terminal to form an intermediate node; first wiring connected to the first terminal; second wiring connected to the fourth terminal and, in a planar view, extending in a direction crossing the first wiring; a first selection transistor connected to the first wiring; a second selection transistor connected to the second wiring; a first well terminal connection line to which a well terminal of the first selection transistor is connected; and a second well terminal connection line to which a well terminal of the second selection transistor is connected.

Abstract: Provided are a rewrite method for a variable resistance element that increases a rewrite count, and a non-volatile storage device using the variable resistance element. In the rewrite method for the variable resistance element, a variable resistance layer is disposed between a first electrode and a second electrode, and a write voltage is applied between the first electrode and the second electrode, thereby causing the resistance between the first electrode and the second electrode to reversibly change. After writing to the variable resistance element, the variable resistance element is read, the read current is measured, the measured read current is compared with a reference current, a condition of the writing is changed on the basis of the comparison results, and thereafter writing to the variable resistance element is performed again.

Abstract: A reconfigurable circuit includes: a first line; a first switch element disposed between the first line and a first power source line of first voltage; a second line; a second switch element disposed between the second line and a second power source line of second voltage which is different from the first voltage; and a resistive switch assembly disposed between the first line and the second line. The resistive switch assembly includes: a first non-volatile resistive switch; and a second non-volatile resistive switch whose first end is coupled to a first end of the first non-volatile resistive switch. The second end of the first non-volatile resistive switch is coupled to the first line, and the second end of the second non-volatile resistive switch is coupled to the second line.

Abstract: A design assistance system according to the present invention assists in designing a circuit to be mounted on a programmable logic integrated circuit including a resistance change element. The design assistance system includes: a memory; and at least one processor coupled to the memory. The processor performs operations. The operations includes: generating rewriting history information indicating a number (count) of changing times of a state of the resistance change element; calculating an abrasion cost of a switch included in the circuit, based on the rewriting history information; and carrying out wiring of the circuit, based on an evaluation function including the abrasion cost.

Abstract: A logic integrated circuit includes a switch cell array. The switch cell array includes: a plurality of first wirings extending in a first direction; a plurality of second wirings extending in a second direction; a switch cell including a unit element including two serially connected resistance-changing elements, and a cell transistor to be connected to a shared terminal of the two resistance-changing elements; and a bit line to which the shared terminal is connected via the cell transistor. Two of the switch cells adjacent to each other in the first direction are each connected to the different first wiring and second wiring, and share the bit line, and a diffusion layer to which the bit line is connected.

Abstract: A numerical information generating apparatus receives information of a programmable logic integrated circuit that includes a plurality of crossbar switches each including resistance change elements, calculates, for each of the plurality of crossbar switches, a base delay that is a delay in which influence of a load capacitance of other crossbar switch is excluded and a correction delay that is a delay caused by influence of a fanout of other crossbar switch, and further calculates a delay of each of the plurality of crossbar switches based on the base delay and the correction delay corresponding to each of the plurality of crossbar switches.

Abstract: A reconfigurable circuit includes: a complementary resistive switch including a first resistive switch, a second resistive switch and a selection transistor, wherein a first terminal of the first resistive switch is connected to a first terminal of the second resistive switch and connected to a first terminal of the selection transistor; a first current source having a first terminal connected to a second terminal of the first resistive switch and a second terminal connected to a ground voltage line; a second current source having a first terminal connected to a second terminal of the second resistive switch and a second terminal connected to the ground voltage line; and a resistor having a first terminal connected to a second terminal of the selection transistor and a second terminal connected to a power voltage line.

Abstract: A reconfigurable circuit includes: a plurality of first lines; one or more second lines; a non-volatile resistive cell coupling one of the first lines with one of the second lines at each cross-point between the first lines and the second lines; and first switch elements including first terminals respectively coupled to the first lines, wherein each of the first switch elements is separately turned on or off in accordance with a control signal applied thereto.

Abstract: A design assistance system including: a logic synthesis unit that receives input of an operation description file of the programmable logic integrated circuit, logically synthesizes the inputted operation description file, and generates a net list by using logic elements included in the programmable logic integrated circuit; an arrangement wiring unit that generates resource information of the programmable logic integrated circuit, arranges the logic elements included in the net list on the basis of the generated resource information, and virtually generates a signal path by laying wires among the arranged logic elements; and a reliability control unit that generates configuration information of the programmable logic integrated circuit on the basis of at least two reliability modes, and outputs the generated configuration information.

Abstract: A semiconductor device which includes: a switch array in which a switch cell including a variable resistance switch is arranged at each location where a plurality of wires constituting a crossbar switch intersect; a first selection circuit that selects all of the variable resistance switches included in the switch array; a second selection circuit that selects any of the variable resistance switches included in the switch array; a reading circuit that reads a state of the variable resistance switch selected by any of the first selection circuit and the second selection circuit; and an error detection circuit that detects, based on a state of the variable resistance switch read by the reading circuit, an error in at least any of the variable resistance switches included in the switch array.

Abstract: A reconfigurable circuit comprising: crossbar switches; wires, each of which is coupled to one output port of one crossbar switch and input ports of the other crossbar switches; at least one inverter inserted on each wire for driving long-distance signal transfer, wherein one or less first inverter is inserted on the wire between two adjacent crossbar switches; one or two second inverters inserted between a crossbar switch input port and its connected wire.

Abstract: A semiconductor device includes: first wires which extend in a first direction; second wires extending in a second direction; a unit element which comprises two variable resistance elements connected in series, and has one end connected to a first wire and the other end connected to a second wire; a first control line for controlling the supply of a voltage to the first wire; a second control line for controlling the supply of a voltage to the second wire; and a cell circuit connected to an intermediate node between the two variable resistance elements and also connected to the first control line and the second control line. The cell circuit has: a cell transistor connected to an intermediate node writing driver which supplies a voltage to the intermediate node; and a cell control circuit which controls an electrical conduction state of the cell transistor.

Abstract: A logic integrated circuit includes a switch cell array. The switch cell array includes: a plurality of first wirings extending in a first direction; a plurality of second wirings extending in a second direction; a switch cell including a unit element including two serially connected resistance-changing elements, and a cell transistor to be connected to a shared terminal of the two resistance-changing elements; and a bit line to which the shared terminal is connected via the cell transistor. Two of the switch cells adjacent to each other in the first direction are each connected to the different first wiring and second wiring, and share the bit line, and a diffusion layer to which the bit line is connected.

Abstract: A logic integrated circuit includes: a three-terminal resistance change switch including a first resistance change switch and a second resistance change switch connected in series; a reading circuit which reads first data based on a resistance state of the first resistance change switch and second data based on a resistance state of the second resistance change switch; and a first error detection circuit which compares the first data with the second data and issue an output based on a result of the comparison.

Abstract: A reconfigurable circuit includes: a first line; a first switch element disposed between the first line and a first power source line of first voltage; a second line; a second switch element disposed between the second line and a second power source line of second voltage which is different from the first voltage; and a resistive switch assembly disposed between the first line and the second line. The resistive switch assembly includes: a first non-volatile resistive switch; and a second non-volatile resistive switch whose first end is coupled to a first end of the first non-volatile resistive switch. The second end of the first non-volatile resistive switch is coupled to the first line, and the second end of the second non-volatile resistive switch is coupled to the second line.