Abstract: A programmable integrated circuit includes: a crossbar switch constituted of a plurality of first wires arranged in a first direction, a plurality of second wires arranged in a second direction intersecting the first direction, and resistance change type elements connecting the first wires and the second wires; an output buffer group constituted of at least two output buffers operating with different drive powers; and a logic circuit group constituted of at least one logic circuit connected to an output of the second wire. The output buffers in the output buffer group is connected to an input of any one of a plurality of the first wires.

Abstract: In order to eliminate an increase in the source potential of a transistor selected during writing or reading, this semiconductor device is equipped with: a variable-resistance type first switch having a first terminal and a second terminal; a variable-resistance type second switch having a third terminal and a fourth terminal, the third terminal being connected to the second terminal to form an intermediate node; first wiring connected to the first terminal; second wiring connected to the fourth terminal and, in a planar view, extending in a direction crossing the first wiring; a first selection transistor connected to the first wiring; a second selection transistor connected to the second wiring; a first well terminal connection line to which a well terminal of the first selection transistor is connected; and a second well terminal connection line to which a well terminal of the second selection transistor is connected.

Abstract: Provided is an integrated circuit that has reduced power consumption. The integrated circuit is provided with: a plurality of first wires one end of each of which is used as an input terminal; a plurality of second wires one end of each of which is used as an output terminal and which are respectively connected to the first wires; a bias wire which is connected to each of the second wires, and which is connected to a power supply or ground; a plurality of switches which connect the first wires or the bias wire and the second wires; and a selection circuit which selects electrical connection between the bias wire and the power supply or ground.

Abstract: A reconfigurable circuit comprising: a complementary resistive switch; a write circuit to configure the complementary resistive switch; a read circuit to get ON/OFF information of the complementary resistive switch; a register to store ON/OFF information of the complementary resistive switch.

Abstract: A reconfigurable circuit comprising: crossbar switches; wires, each of which is coupled to one output port of one crossbar switch and input ports of the other crossbar switches; at least one inverter inserted on each wire for driving long-distance signal transfer, wherein one or less first inverter is inserted on the wire between two adjacent crossbar switches; one or two second inverters inserted between a crossbar switch input port and its connected wire.

Abstract: A reconfigurable circuit includes: a plurality of first lines; one or more second lines; a non-volatile resistive cell coupling one of the first lines with one of the second lines at each cross-point between the first lines and the second lines; and first switch elements including first terminals respectively coupled to the first lines, wherein each of the first switch elements is separately turned on or off in accordance with a control signal applied thereto.

Abstract: A crossbar switch includes a plurality of first wires extending in a first direction and second wires extending in a second direction. The switch includes third wires extending in a third direction and fourth wires extending in a fourth direction. The switch includes switch cells connected to the first and second wires. The first wires are skewed relative to the second and fourth wires, while the third wires are skewed relative to the second and fourth wires. The switch cells are connected to the third and fourth wires, and the third wires are also connected to the switch cells connected to the first wires adjacent to the respective first wires, or alternatively the fourth wires are also connected to the switch cells connected to the second wires adjacent to the respective second wires.

Abstract: A reconfigurable circuit includes first and second wires and two or more paths active at different times. Each path includes: a first NVRS whose first terminal is connected to the first wire; a first transistor whose drain terminal is connected to a second terminal of the first NVRS; a second NVRS whose first terminal is connected to the second terminal of the first NVRS; a second transistor whose source terminal is connected to a second terminal of the second NVRS and whose drain terminal is connected to the second wire; and a 2-input AND circuit whose output is connected to a gate terminal of the first transistor. A time control signal is supplied to a first input of the 2-input AND circuit and a gate terminal of the second transistor. A write control signal is supplied to a second input of the 2-input AND circuit.

Abstract: Provided is an integrated circuit that has reduced power consumption. The integrated circuit is provided with: a plurality of first wires one end of each of which is used as an input terminal; a plurality of second wires one end of each of which is used as an output terminal and which are respectively connected to the first wires; a bias wire which is connected to each of the second wires, and which is connected to a power supply or ground; a plurality of switches which connect the first wires or the bias wire and the second wires; and a selection circuit which selects electrical connection between the bias wire and the power supply or ground.

Abstract: In order to provide a highly reliable crossbar circuit that enables salvation of reversal of a resistive state of a variable resistance element, the semiconductor device has a configuration obtained by parallelly arranging two unit elements, each including variable-resistance two-terminal elements connected in series, the semiconductor device being provided with: a unit element group being connected to a first wiring and a second wiring; a first programming driver that changes, via the first wiring, a resistive state of the two-terminal element constituting the unit element group; a first selection transistor being connected to the first wiring and the first programming driver; a second programming driver that changes, via the second wiring, a resistive state of the two-terminal element constituting the unit element group; and a second selection transistor being connected to the second wiring and the second programming driver.

Abstract: An object of the present invention is to provide a method for effectively performing characterization for circuit verification by static timing analysis, of a programmable logic integrated circuit including a crossbar switch including a resistance-variable element, and a logic circuit logically configured with the crossbar switch, wherein: the programmable logic integrated circuit is divided into a plurality of leaf cells including a plurality of load circuits including a part of the crossbar switch, and a power supply element input to the crossbar switch; the leaf cell is divided into delay paths each including a base leaf cell and a correction leaf cell; and circuit verification is performed based on a delay information library in which a delay time for the base leaf cell and a correction delay for the correction leaf cell are integrated into a delay time for the leaf cell.

Abstract: An object of the present invention is to provide a method for effectively performing characterization for circuit verification by static timing analysis, of a programmable logic integrated circuit including a crossbar switch including a resistance-variable element, and a logic circuit logically configured with the crossbar switch, wherein: the programmable logic integrated circuit is divided into a plurality of leaf cells including a plurality of load circuits including a part of the crossbar switch, and a power supply element input to the crossbar switch; the leaf cell is divided into delay paths each including a base leaf cell and a correction leaf cell; and circuit verification is performed based on a delay information library in which a delay time for the base leaf cell and a correction delay for the correction leaf cell are integrated into a delay time for the leaf cell.

Abstract: An object of the present invention is to provide a logic integrated circuit that increases reliability of configuration information held in a switch while maintaining high tamper resistance and a small chip area. The logic integrated circuit according to the present invention includes: a three-terminal resistance change switch including a first resistance change switch and a second resistance change switch connected in series; a reading circuit which reads first data based on a resistance state of the first resistance change switch and second data based on a resistance state of the second resistance change switch; and a first error detection circuit which compares the first data with the second data and issue an output based on a result of the comparison.

Abstract: The purpose of the present invention is to increase the efficiency with which silicon on a chip is used, and to easily reduce the size of a logic cell. To accomplish the purpose, this reconfigurable circuit includes: a logic memory unit configured from a resistance change element, and positioned distributed into at least two units; a logic unit for referencing the logic memory unit and performing logical operations; and a signal path switching unit for receiving the results of the logical operation of the logic unit and outputting said results to the outside. The logic memory part and the signal path switching part constitute part of a crossbar switching circuit, and share write wiring to the resistance change element.

Abstract: A reconfigurable circuit includes first and second wires and two or more paths active at different times. Each path includes: a first NVRS whose first terminal is connected to the first wire; a first transistor whose drain terminal is connected to a second terminal of the first NVRS; a second NVRS whose first terminal is connected to the second terminal of the first NVRS; a second transistor whose source terminal is connected to a second terminal of the second NVRS and whose drain terminal is connected to the second wire; and a 2-input AND circuit whose output is connected to a gate terminal of the first transistor. A time control signal is supplied to a first input of the 2-input AND circuit and a gate terminal of the second transistor. A write control signal is supplied to a second input of the 2-input AND circuit.

Abstract: In order to provide a crossbar switch type memory circuit designed to be usable in normal circumstances even when a resistance change element is in an adverse state, the present invention is provided with: a first unit including a first column wiring to which one end of a first resistance change element is connected, a first power supply-side transistor for controlling the connection of the first column wiring and a power supply node, a first ground-side transistor, of a reverse operation type to the first power supply-side transistor, for controlling the connection of the first column wiring and a ground node, and a first polarity control line for causing the first power supply-side transistor or the first ground-side transistor to turn on and the other to turn off by a polar signal from a polar signal terminal, the first polarity control line being connected to the control terminals of the first power supply-side transistor and first ground-side transistor; a second unit including a second column wiring to

Abstract: A reconfigurable circuit comprising: a first level crossbar switch that has first non-volatile resistive switches; a second level crossbar switch that has second non-volatile resistive switches; and a first wire and third non-volatile resistive switches that are used for redundancy, wherein input wires of the second level crossbar switch are connected to output wires of the first level crossbar switch one-to-one, and input wires of the first level crossbar switch and output wires of the second level crossbar switch are connected to the first wire through the third non-volatile resistive switches.

Abstract: In order to stably write data into a magnetic memory that uses in-plane current-induced perpendicular switching of magnetization to write data, the magnetic memory includes a recording layer formed as a perpendicular magnetization film, an adjacent layer joined to an upper surface or a lower surface of the recording layer, an external magnetic field application part configured to apply a first external magnetic field to the recording layer in a first direction which is an in-plane direction of the recording layer, and a current application part configured to allow a write current to flow through the adjacent layer in the first direction or a second direction which is opposite to the first direction. The external magnetic field application part is configured to switch a direction of a second external magnetic field applied in a direction perpendicular to the first direction in accordance with a direction of the write current.

Abstract: The invention is to provide a compact reconfigurable circuit implementing a LUT and a “hard” circuit. The present invention provides a reconfigurable circuit comprising: first wires disposed in a first direction; a second wire disposed in a second direction intersecting the first direction; a power line, a ground line and data input line or data input inverse line coupled to the said first wires one-to-one; a multiplexer, one of whose inputs is connected with the second wire; nonvolatile switch cells utilized to interconnect the first wires and second wire at the crosspoints, wherein every nonvolatile switch cell is constructed by at least one non-volatile resistive switch.

Abstract: Provided is a programmable logic integrated circuit wherein even if a failure occurs in any resistance-variable element, remedy would be possible and hence the improvement of reliability has been achieved. In a programmable logic integrated circuit comprising resistance-variable elements, when the states of the resistance-variable elements are to be changed according to externally inputted configuration information, a control means uses a reading means to read the states of the respective resistance-variable elements, and then uses a writing means to change only the states of resistance-changing elements that are different from a state indicated by the configuration information.