Abstract: A variable resistance layer between a first electrode and a second electrode includes: a first variable resistance layer contacting the first electrode; and a second variable resistance layer contacting the second electrode and having a lower degree of oxygen deficiency than the first variable resistance layer. A principal face of the first variable resistance layer which is close to the second variable resistance layer is flat. The second variable resistance layer is in contact with both the first variable resistance layer and the second electrode in a polygonal region including a vertex inward of an outline of the variable resistance layer and vertices along the outline when seen from a direction perpendicular to the principal face of the variable resistance layer, and is not in contact with at least one of the first variable resistance layer and the second electrode in a region outside the region inside the polygon.

Abstract: The present invention provides a system comprising a semiconductor device, a method of controlling the semiconductor device in the system, and a method of manufacturing the semiconductor device in the system. The semiconductor device includes: a semiconductor region located in a semiconductor layer formed on an isolating layer; an ONO film on the semiconductor region; bit lines on either side of the semiconductor region, which are located in the semiconductor layer, and are in contact with the isolating layer; a device isolating region on two different sides of the semiconductor region from the sides on which the bit lines are located, the device isolating region being in contact with the isolating layer; and a first voltage applying unit that is coupled to the semiconductor region. In this semiconductor device, the semiconductor region is surrounded by the bit lines and the device isolating region, and is electrically isolated from other semiconductor regions.

Abstract: A method of manufacturing a semiconductor device includes forming a silicon nitride film having an opening portion on a semiconductor substrate, forming a silicon oxide film on the silicon nitride film and on a side face of the opening portion, performing an etching treatment to the silicon oxide film so that a sidewall is formed on the side face of the opening portion, forming a trench on the semiconductor substrate with use of the sidewall and the silicon nitride film as a mask, and forming an insulating layer in the trench. The step of forming the silicon oxide film includes oxidizing the silicon nitride film with a plasma oxidation method or a radical oxidation method.

Abstract: Provided is a method for manufacturing a variable resistance nonvolatile semiconductor memory element, and a nonvolatile semiconductor memory element which make it possible to operate at a low voltage and high speed when initial breakdown is caused, and exhibit favorable diode element characteristics. The method for manufacturing the nonvolatile semiconductor memory element includes, after forming a top electrode of a variable resistance element and at least before forming a top electrode of an MSM diode element, oxidizing to insulate a portion of a variable resistance film in a region around an end face of a variable resistance layer.

Abstract: A nonvolatile memory element includes a variable resistance layer located between a lower electrode and an upper electrode and having a resistance value that reversibly changes based on electrical signals applied between these electrodes. The variable resistance layer includes at least two layers: a first variable resistance layer including a first transition metal oxide; and a second variable resistance layer including a second transition metal oxide and a transition metal compound. The second transition metal oxide has an oxygen content atomic percentage lower than an oxygen content atomic percentage of the first transition metal oxide, the transition metal compound contains either oxygen and nitrogen or oxygen and fluorine, and the second transition metal oxide and the transition metal compound are in contact with the first variable resistance layer.

Abstract: A nonvolatile memory device includes a plurality of nonvolatile memory elements each having an upper electrode, a variable resistance layer, and a lower electrode; a first insulating layer embedding the plurality of nonvolatile memory elements, and ranging from a lowermost part of the lower electrode to a position higher than an uppermost part of the upper electrode in each of the nonvolatile memory elements; a second insulating layer being formed on the first insulating layer, and having an average size of vacancies larger than an average size of vacancies included in the first insulating layer, or having an average carbon concentration higher than an average carbon concentration of the first insulating layer; and a conductive layer penetrating the second insulating layer and a part of the first insulating layer and being connected to at least one of the upper electrodes included in the nonvolatile memory elements.

Abstract: The present invention provides a semiconductor device that has a shorter distance between the bit lines and easily achieves higher storage capacity and density. The semiconductor device includes: first bit lines formed on a substrate; an insulating layer that is provided between the first bit lines and in a groove in the substrate, and has a higher upper face than the first bit lines; channel layers that are provided on both side faces of the insulating layer, and are coupled to the respective first bit lines; and charge storage layers that are provided on the opposite side faces of the channel layers from the side faces on which the insulating layers are formed.

Abstract: A nonvolatile memory element including: a first electrode; a second electrode; a variable resistance layer that is between the first electrode and the second electrode and includes, as stacked layers, a first variable resistance layer connected to the first electrode and a second variable resistance layer connected to the second electrode; and a side wall protecting layer that has oxygen barrier properties and covers a side surface of the variable resistance layer. The first variable resistance layer includes a first metal oxide and a third metal oxide formed around the first metal oxide and having an oxygen deficiency lower than that of the first metal oxide, and the second variable resistance layer includes a second metal oxide having an oxygen deficiency lower than that of the first metal oxide.

Abstract: A current steering element (100) formed such that the current steering element covers a lower opening (105) of a via hole (104) formed in an interlayer insulating layer (102), comprises: a corrosion-suppressing layer (106) formed on a lower side of a lower opening of the via hole such that the corrosion-suppressing layer covers an entire portion of the lower opening; a second electrode layer (108) formed under the corrosion-suppressing layer and comprising a material different from a material of the corrosion-suppressing layer; a current steering layer (110) formed under the second electrode layer such that the current steering layer is physically in contact with the second electrode layer; and a first electrode layer (112) formed under the current steering layer such that the first electrode layer is physically in contact with the current steering layer; and the first electrode layer, the current steering layer and the second electrode layer constitute one of a MSM diode and a MIM diode.

Abstract: A method of manufacturing a semiconductor device includes forming a silicon nitride film having an opening portion on a semiconductor substrate, forming a silicon oxide film on the silicon nitride film and on a side face of the opening portion, performing an etching treatment to the silicon oxide film so that a sidewall is formed on the side face of the opening portion, forming a trench on the semiconductor substrate with use of the sidewall and the silicon nitride film as a mask, and forming an insulating layer in the trench. The step of forming the silicon oxide film includes oxidizing the silicon nitride film with a plasma oxidation method or a radical oxidation method.

Abstract: A method of designing a cross-point non-volatile memory device including memory elements arranged in (N×M) matrix, each of the memory elements including a variable resistance element and a bidirectional current steering element connected in series with the variable resistance element, the method comprises the step of: when an absolute value of a low-resistance state writing voltage is VR and an absolute value of a current flowing through the variable resistance element having changed to a low-resistance state by application of the low-resistance state writing voltage to both ends of the variable resistance element in a high-resistance state is Ion, and a relationship between a voltage V0 applied to both ends of the bidirectional current steering element and a current I flowing through the bidirectional current steering element is approximated as |V0|=a×Log(I)+b, deciding N, M, VR, Ion, a, and b such that b?VR/2>a×[Log {(N?1)×(M?1)}?Log(Ion)] is satisfied (S101).

Abstract: The present invention provides a system comprising a semiconductor device, a method of controlling the semiconductor device in the system, and a method of manufacturing the semiconductor device in the system. The semiconductor device includes: a semiconductor region located in a semiconductor layer formed on an isolating layer; an ONO film on the semiconductor region; bit lines on either side of the semiconductor region, which are located in the semiconductor layer, and are in contact with the isolating layer; a device isolating region on two different sides of the semiconductor region from the sides on which the bit lines are located, the device isolating region being in contact with the isolating layer; and a first voltage applying unit that is coupled to the semiconductor region. In this semiconductor device, the semiconductor region is surrounded by the bit lines and the device isolating region, and is electrically isolated from other semiconductor regions.

Abstract: A method of manufacturing a semiconductor device according to the present invention includes: forming a lower electrode above a substrate; forming, above the lower electrode, a first variable resistance layer comprising a first metal oxide; forming a step region in the first variable resistance layer by collision of ions excited by plasma; removing residue of the first variable resistance layer created in the forming of the step region; forming a second variable resistance layer which covers the step region of the first variable resistance layer, comprises a second metal oxide having a degree of oxygen deficiency lower than a degree of oxygen deficiency of the first metal oxide, and has a bend on a step formed along an edge of the step region; and forming an upper electrode above the second variable resistance layer.

Abstract: A non-volatile memory device includes: a memory cell array including a plurality of memory cells each including a first variable resistance element and a first current steering element and a parameter generation circuit including a reference cell including a second variable resistance element and a second current steering element having the same current density-voltage characteristic as that of the first current steering element, wherein a conductive shorting layer for causing short-circuiting between the electrodes is formed on the side surfaces of the second variable resistance element.

Abstract: The present invention provides a semiconductor device that has a shorter distance between the bit lines and easily achieves higher storage capacity and density, and a method of manufacturing such a semiconductor device. The semiconductor device includes: first bit lines formed on a substrate; an insulating layer that is provided between the first bit lines on the substrate, and has a higher upper face than the first bit lines; channel layers that are provided on both side faces of the insulating layer, and are coupled to the respective first bit lines; and charge storage layers that are provided on the opposite side faces of the channel layers from the side faces on which the insulating layers are formed.

Abstract: A non-volatile memory device includes: a memory cell array including a plurality of memory cells each including a variable resistance element and a first current steering element; and a current steering element parameter generation circuit. The current steering element parameter generation circuit includes: a third line placed between a substrate and a second interlayer dielectric; a fourth line placed above the second interlayer dielectric; and a second current steering element which is connected between the third line and the fourth line without the variable resistance element being interposed therebetween when the variable resistance element is removed between the third line and the fourth line and has the same non-linear current steering characteristics as the first current steering element.

Abstract: A suspension control apparatus includes a single-wheel model calculating unit that calculates a sprung speed and a stroke speed using a single-wheel model on the basis of a wheel speed variation detected by a wheel speed sensor and a damper control unit that controls the damping force of a variable damping force damper by setting a skyhook control target current and an unsprung vibration damping control target current of the variable damping force damper on the basis of the calculated sprung speed and stroke speed. When a slip determining unit determines that the wheel is in a slipping state based on deviation of a value detected by the wheel speed sensor from a wheel speed estimated by the vehicle body speed estimating unit by a predetermined value or more, the damper control unit suppresses skyhook and unsprung vibration damping control by fixing or gradually decreasing the control target currents.

Abstract: Provided are a nonvolatile memory device which can suppress non-uniformity in initial breakdown voltages among nonvolatile memory elements and prevent reduction of yield, and a manufacturing method thereof. The nonvolatile memory device includes a nonvolatile memory element (108) having a stacked-layer structure in which a resistance variable layer (106) is parallel to a main surface of a substrate (117) and is planarized, and a plug (103) electrically connected to either a first electrode (105) or a second electrode (107), and an area of an end surface of a plug (103) at which the plug (103) and the nonvolatile memory element (108) are connected together, the end surface being parallel to the main surface of the substrate (117), is greater than a cross-sectional area of a cross-section of a first transition metal oxide layer (115) which is an electrically-conductive region, the cross-section being parallel to the main surface of the substrate (117).

Abstract: An object of the present invention is to provide a method for manufacturing a variable resistance nonvolatile semiconductor memory element which can operate at a low voltage and high speed when initial breakdown is caused, and inhibit oxidization of a contact plug. The method for manufacturing the variable resistance nonvolatile semiconductor memory element, which includes a bottom electrode, a variable resistance layer, and a top electrode which are formed above a contact plug, includes oxidizing to insulate an end portion of the variable resistance layer prior to forming a bottom electrode by patterning a first conductive film.

Abstract: A variable resistance element comprises, when M is a transition metal element, O is oxygen, and x and y are positive numbers satisfying y>x; a lower electrode; a first oxide layer formed on the lower electrode and comprising MOx when a content ratio of O with respect to M is x; a second oxide layer formed on the first oxide layer and comprising MOy when a content ratio of O with respect to M is y; an upper electrode formed on the second oxide layer; a protective layer formed on the upper electrode and comprising an electrically conductive material having a composition different from a composition of the upper electrode; an interlayer insulating layer formed to cover the protective layer; and an upper contact plug formed inside an upper contact hole penetrating the interlayer insulating layer.