Abstract: An optical transmitter includes: an optical modulator that includes a Mach-Zehnder interferometer, a first phase shift segment, and a second phase shift segment, the first phase shift segment and the second phase shift segment each being configured to shift a phase of light propagating through an optical path of the Mach-Zehnder interferometer; and a drive circuit that generates a signal for driving the optical modulator. The drive circuit includes: a first circuit that generates a first electric signal from an input signal indicating transmission data; and a second circuit that generates a second electric signal that emphasizes an edge of the first electric signal based on the input signal. The drive circuit provides the first electric signal to the first phase shift segment and provides the second electric signal to the second phase shift segment.

Abstract: An arithmetic processing apparatus includes a memory and a processor. The processor coupled to memory and configured to determine an individual not to be evolved to an individual of a second generation from among a plurality of individuals in a first generation based on a predetermined reference for calculation completion of fitness calculation for each of the plurality of individuals, the second generation being a generation next to the first generation, and determine to cause the determined individual to evolve to an individual of a generation next or subsequent to the second generation.

Abstract: A method includes: generating a plurality of individuals of a current generation in accordance with a plurality of individuals of a previous generation to acquire values of an objective function for individuals each representing a variable by evolutionary computation; calculating, for each of partial individuals of the plurality of individuals of the current generation generated by the generating processing, a first value of the objective function by a predetermined method; approximately calculating, for each of the plurality of individuals of the current generation, a second value of the objective function with lower precision than the predetermined method; computing a fitness difference representing a difference between the plurality of individuals of the current generation in accordance with the first value or the second value; and controlling the precision of the approximate calculation based on the fitness difference and a precision difference between the first value and the second value.

Abstract: An arithmetic processing apparatus includes a memory; and a processor coupled to the memory and the processor configured to execute a prediction process and a search process in an evolutionary calculation process for searching an optimum value of inputs by calculating an objective function based on eigen solutions for inputs and repeatedly calculating the objective function, wherein the prediction process includes predicting a range of an eigen solution for a second input, which satisfies a predetermined eigen solution condition, based on a first eigen solution for a first input when searches an optimum value of inputs by calculating an objective function based on eigen solutions for inputs and repeatedly calculating the objective function, and the search process includes searching a second eigen solution for the second input, which satisfies the eigen solution condition, in the predicted range of the eigen solution.

Abstract: A non-transitory computer-readable recording medium storing an evolutionary computation program in which a processor included in a computer executes a process, the process includes calculating fitness of a plurality of individuals based on a plurality of input in parallel in one generation, discontinuing, when a predetermined reference value at an end of a search for an eigensolution used to calculate the fitness of each of the plurality of individuals exceeds a threshold value, calculation of an individual in which the predetermined reference value exceeds the threshold value, and assigning an estimated fitness value to the individual for which the calculation is discontinued.

Abstract: An arithmetic processing apparatus includes a memory and a processor. The processor coupled to memory and configured to determine an individual not to be evolved to an individual of a second generation from among a plurality of individuals in a first generation based on a predetermined reference for calculation completion of fitness calculation for each of the plurality of individuals, the second generation being a generation next to the first generation, and determine to cause the determined individual to evolve to an individual of a generation next or subsequent to the second generation.

Abstract: An information processing apparatus, includes a memory; and a processor coupled to the memory and configured to: when an eigen solution of an equation of a first generation is calculated in an evolutionary computation for calculating an eigen solution of an equation by using a plurality of input parameters, calculate function values of a function in the equation as first plural function values for partial input parameters of the plurality of input parameters, predict eigen solution candidates for the first plural function values based on combinations of second plural function values for the partial input parameters and eigen solutions calculated by using the plurality of input parameters in a plurality of generations before the first generation, and calculate a solution of the equation in vicinity of the input parameters corresponding to the eigen solution candidates.

Abstract: An information processing apparatus, a non-transitory computer-readable storage medium storing a program, and an information processing method are described. In an embodiment, provided is a solution to suppress increases of the amount of computational complexity of repetitions of each generation due to prediction with low precision. For example, an information processing apparatus includes: a memory configured to store program instructions; and a processor configured to execute the program instruction for evolutionary computation that searches an optimum value of the input parameters, the evolutionary computation being configured to repetitively calculate an objective function computed based on eigen solutions for input parameters, the program instructions including: a prediction processing; a first calculation processing; a second calculation processing; and a decision processing.

Abstract: A method includes: generating a plurality of individuals of a current generation in accordance with a plurality of individuals of a previous generation to acquire values of an objective function for individuals each representing a variable by evolutionary computation; calculating, for each of partial individuals of the plurality of individuals of the current generation generated by the generating processing, a first value of the objective function by a predetermined method; approximately calculating, for each of the plurality of individuals of the current generation, a second value of the objective function with lower precision than the predetermined method; computing a fitness difference representing a difference between the plurality of individuals of the current generation in accordance with the first value or the second value; and controlling the precision of the approximate calculation based on the fitness difference and a precision difference between the first value and the second value.

Abstract: A driving circuit includes a first transistor that includes a first terminal, a second terminal, and a third terminal; a second transistor having a fourth terminal, a fifth terminal, and a sixth terminal; and an output portion that outputs a signal between the second transistor and a second current source to a light emitting element, wherein the first terminal is coupled to a first power source, a signal is input to the second terminal, and the third terminal is grounded through a first current source which is different from the second current source, and the fourth terminal is coupled to a second power source which is the same as or different from the first power source via the second current source, the fifth terminal is coupled to a voltage source or a bias circuit, and the sixth terminal is coupled between the first transistor and the first current source.

Abstract: An arithmetic processing apparatus includes a memory; and a processor coupled to the memory and the processor configured to execute a prediction process and a search process in an evolutionary calculation process for searching an optimum value of inputs by calculating an objective function based on eigen solutions for inputs and repeatedly calculating the objective function, wherein the prediction process includes predicting a range of an eigen solution for a second input, which satisfies a predetermined eigen solution condition, based on a first eigen solution for a first input when searches an optimum value of inputs by calculating an objective function based on eigen solutions for inputs and repeatedly calculating the objective function, and the search process includes searching a second eigen solution for the second input, which satisfies the eigen solution condition, in the predicted range of the eigen solution.

Abstract: There is provided a driver circuit configured to drive a light emitting device, the driver circuit including an asymmetric circuit configured to receive an input signal and include a first capacitor coupled to the input signal and a signal having a fixed electric potential so as to generate a first signal, a delay circuit configured to receive the input signal and delay the input signal so as to generate a second signal, and an adder circuit configured to add the first signal and the second signal so as to generate a drive signal for driving the light emitting device.

Abstract: A driving circuit includes a first transistor that includes a first terminal, a second terminal, and a third terminal; a second transistor having a fourth terminal, a fifth terminal, and a sixth terminal; and an output portion that outputs a signal between the second transistor and a second current source to a light emitting element, wherein the first terminal is coupled to a first power source, a signal is input to the second terminal, and the third terminal is grounded through a first current source which is different from the second current source, and the fourth terminal is coupled to a second power source which is the same as or different from the first power source via the second current source, the fifth terminal is coupled to a voltage source or a bias circuit, and the sixth terminal is coupled between the first transistor and the first current source.

Abstract: A signal recovery circuit includes, a voltage controlled oscillator that generate a clock signal, a phase frequency comparison circuit that compares phases of the clock signal and an received input signal and compares frequencies of the clock signal and the received input signal, a voltage adjustment circuit that adjusts the phase of the clock signal by adjusting control voltage of the voltage controlled oscillator based on an output of the phase frequency comparison circuit, and a control circuit that acquires an amplitude of the received input signal, detects continuation of the same sign in the received input signal based on the acquired amplitude, stops an adjustment of the phase of the clock signal generated by the voltage controlled oscillator when the continuation of the same sign is detected, and executes adjustment of the phase of the clock signal when the continuation of the same sign is stopped.

Abstract: A signal recovery circuit includes, a voltage controlled oscillator that generate a clock signal, a phase frequency comparison circuit that compares phases of the clock signal and an received input signal and compares frequencies of the clock signal and the received input signal, a voltage adjustment circuit that adjusts the phase of the clock signal by adjusting control voltage of the voltage controlled oscillator based on an output of the phase frequency comparison circuit, and a control circuit that acquires an amplitude of the received input signal, detects continuation of the same sign in the received input signal based on the acquired amplitude, stops an adjustment of the phase of the clock signal generated by the voltage controlled oscillator when the continuation of the same sign is detected, and executes adjustment of the phase of the clock signal when the continuation of the same sign is stopped.

Abstract: A signal recovery circuit includes an oscillator that generates a first clock of which a frequency is variable, and a feedback circuit that controls the oscillator to synchronize the first clock with input data, depending on a phase relationship between the input data and the first clock, the feedback circuit including a control portion that controls the oscillator depending on the phase relationship between the input data and the first clock, a first phase detection circuit that generates a clock phase control signal depending on the phase relationship between the input data and the first clock, an output data generation circuit that generates output data by latching the input data at a change edge of the first clock, and a lock detection circuit that outputs a lock detection signal indicating whether a state is a lock state or a non-lock state.

Abstract: A drive circuit of a light emitting element, the drive circuit includes: an input terminal configured to receive an input signal; an output terminal configured to output a signal based on the input signal as a drive signal to the light emitting element; and a main body circuit configured to generate the drive signal by carrying out timing correction to reduce a difference from a standard delay value for rising or falling of a plurality of signal patterns of the input signal regarding a timing of rising of a first signal subsequent to a first signal pattern in the plurality of signal patterns or a timing of falling of a second signal subsequent to a second signal pattern in the plurality of signal patterns.

Abstract: There is provided a driver circuit configured to drive a light emitting device, the driver circuit including an asymmetric circuit configured to receive an input signal and include a first capacitor coupled to the input signal and a signal having a fixed electric potential so as to generate a first signal, a delay circuit configured to receive the input signal and delay the input signal so as to generate a second signal, and an adder circuit configured to add the first signal and the second signal so as to generate a drive signal for driving the light emitting device.

Abstract: A drive circuit of a light emitting element, the drive circuit includes: an input terminal configured to receive an input signal; an output terminal configured to output a signal based on the input signal as a drive signal to the light emitting element; and a main body circuit configured to generate the drive signal by carrying out timing correction to reduce a difference from a standard delay value for rising or falling of a plurality of signal patterns of the input signal regarding a timing of rising of a first signal subsequent to a first signal pattern in the plurality of signal patterns or a timing of falling of a second signal subsequent to a second signal pattern in the plurality of signal patterns.

Abstract: A signal recovery circuit includes an oscillator configured to control a frequency of generating first clock, and a feedback circuit configured to control the oscillator in order that input data is synchronized with the first clock in accordance with a phase relation between the input data and the first clock, wherein the feedback circuit includes a controller configured to control the oscillator in accordance with the phase relation between the input data and the first clock, a first phase detector configured to generate a clock phase control signal in accordance with the phase relation between the input data and the first clock, and a state detection circuit configured to detect whether the signal recovery circuit is in a locked state or an unlocked state, based on a magnitude of an amplitude of a first component or a second component of the clock phase control signal.