Abstract: An emphasis circuit includes: an applying circuit to add an emphasis signal to an input differential signal; a feedback path to feed back a differential output of the applying unit; a comparing circuit to compare a direct current component level of a positive phase signal and of a negative phase signal of the differential signal; a direct current component level controlling circuit to control a direct current component level of at least one of the positive phase signal and the negative phase signal; a delay unit circuit to add a delay to at least one of the fed-backed differential signal to generate the emphasis signal and inputs the emphasis signal into the applying unit; and a dummy load coupled to a positive phase signal output or a negative phase signal output of the applying unit.

Abstract: An emphasis circuit includes: an applying circuit to add an emphasis signal to an input differential signal; a feedback path to feed back a differential output of the applying unit; a comparing circuit to compare a direct current component level of a positive phase signal and of a negative phase signal of the differential signal; a direct current component level controlling circuit to control a direct current component level of at least one of the positive phase signal and the negative phase signal; a delay unit circuit to add a delay to at least one of the fed-backed differential signal to generate the emphasis signal and inputs the emphasis signal into the applying unit; and a dummy load coupled to a positive phase signal output or a negative phase signal output of the applying unit.

Abstract: There is provided an optical receiving device for deriving a signal using for data identification. The optical receiving device includes a demodulator for demodulating a modulated optical signal to an demodulated optical signal, a convertor for converting the demodulated optical signal to a first and a second electric signals, a generator for generating a complement signal by summing the first electric signal of a normal in phase component and the second electric signal of a reverse in phase component, and a suppressor for suppressing, by the use of the complement signal, a variation of potential which appears in a data signal at a time of phase changing of the modulated optical signal, the data signal being a difference of the normal in phase component and the reverse in phase component.

Abstract: A signal shaping circuit includes an operational circuit that provides weights to a first signal input to a first input element and a second signal input to a second input element, adds or subtracts the second signal to or from the first signal, and outputs a signal obtained by adding or subtracting the second signal to or from the first signal; a divider that divides the signal output from the operational circuit into signals, causes one of the divided signal to be input to the second input element, and outputs the other of the divided signal; a delay element that delays the signal output from the operational circuit and to be input to the divider or the signal output from the divider and to be input to the second input element; and an adjuster that adjusts at least one of the weights provided to the first and second signals.

Abstract: An optical communication apparatus includes a receiver configured to receive an optical signal transmitted from an optical transmitting apparatus; a detector configured to detect a predetermined pattern signal included in the optical signal; a calculator configured to calculate, based on a waveform of the predetermined pattern signal, an amount of dispersion of the predetermined pattern signal; and a compensator configured to compensate for dispersion according to the amount of dispersion.

Abstract: In an optical receiver, a light receiving element receives the optical packet signals and converts the optical packet signals to electrical signals. A bias voltage supply section supplies bias voltage to the light receiving element. A monitoring section monitors an input level of each optical packet signal or each electrical signal and transmits a monitored value to the bias voltage supply section. In addition, the bias voltage supply section temporarily increases the bias voltage according to magnitude of the monitored value after an end of receiving of each optical packet signal.

Abstract: A parallel-serial converter includes a converter circuit that converts parallel data into serial data; a first sampling circuit that samples, according to a first clock signal, the serial data output from the converter circuit; a second sampling circuit that samples, according to a second clock signal that is an inverse of the first clock signal, replica data that is synchronized with the serial data; a third sampling circuit that samples, according to plural third signals respectively having different phases, output from the second sampling circuit; and a control circuit that controls sampling timing of the first sampling circuit, based on each output from the third sampling circuit.

Abstract: A signal shaping circuit that shapes a drive signal and includes a main-signal amplifying circuit that amplifies the drive signal; a preemphasis generating circuit that symmetrically emphasizes a rising portion and a falling portion of the drive signal; a current source that is provided in the main-signal amplifying circuit; and a condenser that couples the main-signal amplifying circuit and the preemphasis generating circuit.

Abstract: A plurality of inductors are connected in series between a load resistor and a first transistor, and a plurality of second transistors provided in parallel are connected to the plurality of inductors.

Abstract: There is provided a parallel-serial converter including a selector to convert parallel data to serial data, a flip-flop to which the serial data are input so as to latch the serial data, a generator to generate replica data simulating the serial data, a detector to detect a first switching point of the replica data and a second switching point subsequent to the first switching point, and a controller to control relative timings of timing converted to the serial data in the selector and timing when the serial data is latched in the flip-flop, based on the first switching point and the second switching point.

Abstract: A light modulation device capable of stabilizing a phase set in phase modulation processing and improving optical communication quality. A phase modulator is provided for each of plural branched input lights and performs phase modulation of the input light. A phase shifter is provided at the upstream or downstream of the phase modulator and shifts a phase of the input light or of the phase-modulated light. A light interference section causes the output lights from the light modulator to interfere with each other to generate a multilevel phase modulated signal and interference light having a phase state different from that of the modulated signal. A monitor receives the interference light and outputs an electric signal according to the intensity. A phase shift controller generates a phase control signal based on the electric signal and applies the signal to the shifter to control the phase shift amount to be set by the shifter.

Abstract: An emphasis signal generation circuit includes a phase shifter configured to delay a signal, an adder/subtractor configured to perform addition/subtraction of a first signal and a second signal at a predetermined ratio, the ratio being freely variable, and an amplitude adjuster configured to perform adjustment of an amplitude of a signal with an adjustment amount of the amplitude being freely variable. An input signal to the emphasis signal generation circuit is input to the adder/subtractor as the first signal. Meanwhile, an emphasis component signal obtained by delaying the input signal by the phase shifter and adjusting the amplitude of the delayed input signal is input to the adder/subtractor as the second signal.

Abstract: A parallel data output device includes a first latch circuit that latches and outputs one of at least two data signals input in parallel in accordance with a first clock signal; a second latch circuit that latches and outputs another of the at least two data signals in accordance with a second clock signal; and a phase set circuit that shifts at least one of a phase of the first clock signal and a phase of the second clock signal based on the phase of the first clock signal and the phase of the second clock signal.

Abstract: In a parallel-serial converter circuit of a multistage configuration, there is formed a clock propagation path so that when multistage connected data converters are operated according to the timing of a clock signal, a reference clock signal or a clock signal in which the reference clock signal has been frequency-converted, is given sequentially to the data converter of the first stage up to the data converter of the final stage. As a result, even in a case where variations occur in power supply voltage, timing deviation of data signals and clock signals input to the data converters of the second and subsequent stages can be suppressed, and parallel-serial conversion of high-speed data signals can be reliably executed.

Abstract: An amplifier circuit includes a first amplifier amplifying an input signal and outputting a first amplified signal, a second amplifier amplifying the first amplified signal and outputting a second amplified signal, and a feedback circuitry feeding back the second amplified signal to the input of the second amplifier. The feedback circuitry includes a feedback transistor that keeps the input level of the second amplifier constant.

Abstract: A driving circuit for driving a diode includes at least one differential pair including a first output node and a second output node and configured to switch an output current, a current source configured to adjust the output current, a dummy load coupled to the second output node, a first termination resistor coupled between the first output node and a termination ground, and a second termination resistor coupled between the second output node and the termination ground. The output current is supplied to the diode through the first output node by at least one differential pair.

Abstract: A communication apparatus time-division multiplexes a first signal transmitted at a first bit rate and a second signal transmitted at a second bit rate which is an integer multiple of the first bit rate, and sends out the first signal and the second signal to one line. The communication apparatus includes a pulse generating unit and a pulse superimposing unit. The pulse generating unit generates repetitive pulses having a width equal to a width of the first signal. The pulse superimposing unit superimposes the pulses generated by the pulse generating unit on the second signal.

Abstract: A driver for shaping a drive signal includes a pre-emphasis circuit, an offset adjustment circuit, and an amplifier. The pre-emphasis circuit symmetrically emphasizes a rising edge portion and a falling edge portion of the drive signal. The offset adjustment circuit applies a direct-current offset to the drive signal. The amplifier amplifies the drive signal with the direct-current offset adjusted by the adjustment circuit. The amplifier has an input-output characteristic with a nonlinear portion. The offset adjustment circuit adjusts the direct-current offset so that the drive signal is amplified in the nonlinear portion.

Abstract: A drive circuit includes a duty cycle adjusting circuit that changes the duty cycle of a first signal; and a calculating circuit that with respect to signals that include the first signal for which the duty cycle has been adjusted and a second signal having a phase and amplitude that differ from that of the first signal, performs any one of subtracting one of the signals from the other signal and adding the signals.

Abstract: A driver circuit includes a plurality of delay circuits and an inverter. The plurality of delay circuits delay branched driving signals. The inverter inverts at least one of the branched driving signals. At least one of the plurality of delay circuits is at least one variable delay circuit delaying a variable amount of delay. The output driving signal is output by combining the inverted signal of the branched driving signal output via at least one inverter and at least one non-inverted signal of the branched driving signals output from the delay circuits.