Abstract: A driving circuit for driving a diode includes at least one differential pair including a first output node and a second output node and configured to switch an output current, a current source configured to adjust the output current, a dummy load coupled to the second output node, a first termination resistor coupled between the first output node and a termination ground, and a second termination resistor coupled between the second output node and the termination ground. The output current is supplied to the diode through the first output node by at least one differential pair.

Abstract: A timing signal generation circuit includes: a phase comparison circuit to detect a phase difference between an input signal and a recovery clock; a control voltage signal generation unit to generate two phase differential control voltage signals, based on the detected phase difference; a timing detection circuit to detect timing in which the control voltage signals are inverted, and generate quadrant information of the phase difference of the control voltage signals and an inverted timing signal; a synthesized phase selection circuit to select clocks of two phases which are used for phase interpolation for each predetermined angle, from clocks of a plurality of phases, and generate a phase control signal for the phase interpolation, based on the control voltage signals and the quadrant information; and a phase synthesis circuit to generate the recovery clock by synthesizing the selected clocks of two phases, based on the phase control signal.

Abstract: An emphasis signal generating circuit includes: a branch circuit configured to split a signal into a plurality of paths; a delay circuit provided in one or more of the paths into which the signal has been split by the branch circuit, the delay circuit being configured to delay one or more signals; a phase compensation circuit provided in one or more of the paths into which the signal has been split by the branch circuit, the phase compensation circuit having such characteristics that a transmission intensity of a signal is low in a low frequency band and is high in a high frequency band; and an addition/subtraction circuit configured to perform addition and/or subtraction of signals from the plurality of paths and output a result.

Abstract: A light emitting element drive circuit includes: a plurality of signal paths that respectively propagate a plurality of signals obtained by branching an input signal, a plurality of filters different in a frequency band to pass a signal; one or more amplifiers configured to amplify a signal, one or more delay circuits configured to delay a signal, and an addition circuit that adds a plurality of signals, the filter different in the frequency band being arranged in each of the plurality of signal paths, the delay circuit being arranged in one or more of the plurality of signal paths relatively low in the frequency band, the amplifier being arranged in one or more of the plurality of signal paths relatively high in the frequency band, and an output end of each of the plurality of signal paths being coupled to the addition circuit.

Abstract: A phase interpolation clock generator includes: a phase detector configured to detect a phase difference between an input signal and a clock; a phase control signal generator configured to generate a phase control signal that is inverted for a certain phase difference and changes between a high level and a low level based on the phase difference; a controller configured to generate a combining control signal for combining a plurality of phase clocks and performing phase interpolation based on the phase control signal; an overshoot detector configured to detect overshoot in which the phase control signal rises above the high level; an overshoot canceller configured to lower the phase control signal which rises above the high level at an occurrence of the overshoot; and a phase interpolator configured to generate the clock by combining the plurality of phase clocks in accordance with the combining control signal.

Abstract: A current mirror circuit includes: a reference current circuit including a reference transistor and a constant current source coupled between a high potential source and a low potential source; a first proportional current circuit, including a first transistor that forms a first current mirror circuit with the reference transistor, to generate a first current having a first ratio to a reference current of the reference current circuit; a second proportional current circuit, including a second transistor that forms a second current mirror circuit with the reference transistor, to generate a second current having a second ratio to the reference current; a comparison circuit to output a difference between a drain voltage of the first transistor and a drain voltage of the second transistor; and a current adjustment transistor coupled to a drain of the second transistor and including a gate to which an output of the comparison circuit is applied.

Abstract: An emphasis signal generating circuit includes: a branch and delay unit configured to branch an input signal, delay a branched signal, and output a first delayed signal; a high-frequency extraction unit configured to extract at least one of high-frequency components of the input signal and the first delayed signal to output a high-frequency signal; and an addition and subtraction unit configured to add and subtract the input signal, the first delayed signal, and the high-frequency signal.

Abstract: A timing signal generation circuit includes: a phase comparison circuit to detect a phase difference between an input signal and a recovery clock; a control voltage signal generation unit to generate two phase differential control voltage signals, based on the detected phase difference; a timing detection circuit to detect timing in which the control voltage signals are inverted, and generate quadrant information of the phase difference of the control voltage signals and an inverted timing signal; a synthesized phase selection circuit to select clocks of two phases which are used for phase interpolation for each predetermined angle, from clocks of a plurality of phases, and generate a phase control signal for the phase interpolation, based on the control voltage signals and the quadrant information; and a phase synthesis circuit to generate the recovery clock by synthesizing the selected clocks of two phases, based on the phase control signal.

Abstract: A multi-lane re-timer circuit includes: a clock generation circuit to generate a base clock; and reception circuits to generate a reception clock and receive input data signals from lanes, wherein each of the reception circuits includes: a phase frequency detector to generate phase difference signal and frequency difference signal between the input data signal and the reception clock; a clock data regeneration controller to generate a control signal based on the phase difference signal; a phase rotator to generate the reception clock from the base clock; and a decision circuit to receive the input data signal, and wherein the clock generation circuit includes: an input selector to select a signal; a charge pump to generate a charge signal; a loop filter to remove a high frequency component from the charge signal to output a voltage control signal; and a voltage controlled oscillator to generate the reception clock.

Abstract: A clock data recovery circuit includes: a phase detector circuit configured to generate a phase detection signal indicating a first detection result between a phase of a reception data signal and a phase of a first clock signal; a clock signal generation circuit configured to generate the first clock signal and a second clock signal based on the phase detection signal, the second clock signal having a frequency substantially equal to a frequency of the first clock signal, a phase difference between the first clock signal and the second clock signal being less than 180°; a phase combining circuit configured to combine the first clock signal and the second clock signal in accordance with a phase relation and generate a recovered clock signal; and a recovered data generation circuit configured to sample the reception data signal and generate a recovered data signal based on the recovered clock signal.

Abstract: A light reception circuit includes a direct current (DC) level shift circuit that shifts a DC voltage level of a first signal or a second signal and outputs a third signal or a fourth signal, or outputs both of the third signal and the fourth signal so that a DC voltage level of the first signal output from a cathode of a photodiode that generates a signal by photo conversion and a DC voltage level of the second signal output from an anode of the photodiode agree, and a differential amplifier that amplifies a difference between the third signal and the second signal, between the first signal and the fourth signal, or the third signal and the fourth signal, based on the third signal, the forth signal output from the DC level shift circuit, impedance of the DC level shift circuit being lower than input impedance of the differential amplifier.

Abstract: A phase compensation circuit includes: a first circuit that increases phase characteristic of a specific frequency of an electrical signal; a second circuit that decreases the phase characteristic of the specific frequency of the electrical signal; and a limiting amplifier that amplifies an electrical signal that is processed by at least one of the first circuit and the second circuit.

Abstract: A signal shaping circuit includes an operational circuit that provides weights to a first signal input to a first input element and a second signal input to a second input element, adds or subtracts the second signal to or from the first signal, and outputs a signal obtained by adding or subtracting the second signal to or from the first signal; a divider that divides the signal output from the operational circuit into signals, causes one of the divided signal to be input to the second input element, and outputs the other of the divided signal; a delay element that delays the signal output from the operational circuit and to be input to the divider or the signal output from the divider and to be input to the second input element; and an adjuster that adjusts at least one of the weights provided to the first and second signals.

Abstract: A signal shaping circuit that shapes a drive signal and includes a main-signal amplifying circuit that amplifies the drive signal; a preemphasis generating circuit that symmetrically emphasizes a rising portion and a falling portion of the drive signal; a current source that is provided in the main-signal amplifying circuit; and a condenser that couples the main-signal amplifying circuit and the preemphasis generating circuit.

Abstract: An emphasis signal generating circuit includes: a branch circuit configured to split a signal into a plurality of paths; a delay circuit provided in one or more of the paths into which the signal has been split by the branch circuit, the delay circuit being configured to delay one or more signals; a phase compensation circuit provided in one or more of the paths into which the signal has been split by the branch circuit, the phase compensation circuit having such characteristics that a transmission intensity of a signal is low in a low frequency band and is high in a high frequency band; and an addition/subtraction circuit configured to perform addition and/or subtraction of signals from the plurality of paths and output a result.

Abstract: An amplifier circuit includes an amplifier circuit that emitter-grounds a first transistor that amplifies an input signal; and an emitter-grounded feedback circuit in which a collector of the first transistor is connected to an output line of the amplifier circuit and a base is wiring-connected only to the output line by using a resistor.

Abstract: A driver for shaping a drive signal includes a pre-emphasis circuit, an offset adjustment circuit, and an amplifier. The pre-emphasis circuit symmetrically emphasizes a rising edge portion and a falling edge portion of the drive signal. The offset adjustment circuit applies a direct-current offset to the drive signal. The amplifier amplifies the drive signal with the direct-current offset adjusted by the adjustment circuit. The amplifier has an input-output characteristic with a nonlinear portion. The offset adjustment circuit adjusts the direct-current offset so that the drive signal is amplified in the nonlinear portion.

Abstract: A light emitting element drive circuit includes: a plurality of signal paths that respectively propagate a plurality of signals obtained by branching an input signal, a plurality of filters different in a frequency band to pass a signal; one or more amplifiers configured to amplify a signal, one or more delay circuits configured to delay a signal, and an addition circuit that adds a plurality of signals, the filter different in the frequency band being arranged in each of the plurality of signal paths, the delay circuit being arranged in one or more of the plurality of signal paths relatively low in the frequency band, the amplifier being arranged in one or more of the plurality of signal paths relatively high in the frequency band, and an output end of each of the plurality of signal paths being coupled to the addition circuit.

Abstract: A light reception circuit includes a direct current (DC) level shift circuit that shifts a DC voltage level of a first signal or a second signal and outputs a third signal or a fourth signal, or outputs both of the third signal and the fourth signal so that a DC voltage level of the first signal output from a cathode of a photodiode that generates a signal by photo conversion and a DC voltage level of the second signal output from an anode of the photodiode agree, and a differential amplifier that amplifies a difference between the third signal and the second signal, between the first signal and the fourth signal, or the third signal and the fourth signal, based on the third signal, the forth signal output from the DC level shift circuit, impedance of the DC level shift circuit being lower than input impedance of the differential amplifier.

Abstract: A driver circuit includes a plurality of delay circuits and an inverter. The plurality of delay circuits delay branched driving signals. The inverter inverts at least one of the branched driving signals. At least one of the plurality of delay circuits is at least one variable delay circuit delaying a variable amount of delay. The output driving signal is output by combining the inverted signal of the branched driving signal output via at least one inverter and at least one non-inverted signal of the branched driving signals output from the delay circuits.