Abstract: A wafer carrier includes a base including a generally planar bottom surface and a top surface that includes a plurality of platforms extending above the top surface. The wafer carrier includes a thermal cover defining a plurality of pockets. The thermal cover is configured to be coupled to the base by at least one fastener and the plurality of pockets are arranged such that each pocket of the plurality of pockets is aligned with a corresponding platform of the plurality of the platforms when the thermal cover is supported by a plurality of first pedestals that extend from the top surface of the base. A plurality of second pedestals are located along the plurality of platforms for supporting the one or more wafers, wherein each platform includes at least one second pedestal that extends from a top surface of the platform for supporting one wafer.

Abstract: A wafer carrier assembly as described herein improves thermal control across a top surface thereof to maintain highly controlled deposition locations and thicknesses.

Abstract: A self-centering split substrate carrier that supports a semiconductor substrate in a CVD system includes a first section configured to be centrally located in the split substrate carrier having a top surface with a recessed area for receiving a substrate for CVD processing and comprising a plurality of apertures positioned in an outer surface. A second section formed in a ring-shape having an inner surface configured to receive the first section and an outer surface configured to interface with an edge drive rotation mechanism that rotates the substrate carrier. The inner surface comprising a plurality of boss structures, wherein a respective one of the plurality of boss structures on the inner surface of the second section is configured to fit into a respective one of the plurality of apertures positioned in the outer surface of the first section, so as to improve alignment of the first and the second section of the self-centering split substrate carrier.

Abstract: A substrate reactor with centering pin for epitaxial deposition includes a vacuum chamber and a tube configured to rotate in the vacuum chamber around a tube geometrical center axis. A substrate carrier forming a pocket dimensioned for holding a substrate on a top surface includes an aperture that is centrally located on a bottom surface. The substrate carrier is positioned on and in contact with a top surface of the tube. A centering pin is positioned along a geometrical center axis of rotation of the substrate carrier. The centering pin has a first end positioned in the aperture on the bottom surface of the substrate carrier and a second end fixed inside the reactor so that the substrate carrier rotates around the geometrical center axis of the substrate carrier independent of the geometrical center axis of the tube.

Abstract: A substrate carrier that supports a semiconductor substrate in a chemical vapor deposition system that includes a support having a beveled inner top surface including a top surface and a bottom surface. The top surface has a recessed area for receiving at least one substrate for chemical vapor deposition processing. The bottom surface has a beveled edge that forms a conical interface with the beveled inner top surface of the support at a self-locking angle that prevents substrate carrier movement in a vertical direction at a predetermined temperature equal to a maximum operation temperature. A coefficient of thermal expansion of a material forming the substrate carrier is substantially the same as a coefficient of thermal expansion of a material forming the support.

Abstract: A wafer carrier has a plurality of built-up pockets connected by raised interstitial spaces on a base. Top cover plates are affixed to the base by fasteners and separated from direct thermal contact b302y spacers.

Abstract: A wafer carrier has a plurality of built-up pockets connected by raised interstitial spaces on a base. Top cover plates are affixed to the base by fasteners and separated from direct thermal contact by spacers.

Abstract: A wafer carrier as described and claimed herein includes a thermal cover and a plurality of platforms with corresponding radially inner and outer pedestals.

Abstract: A wafer carrier for use in a system for growing epitaxial layers on one or more wafers by chemical vapor deposition. The wafer carrier includes wafer retention pockets recessed in its body. Each pocket includes a floor surface and a peripheral wall surface surrounding the floor surface and defining a periphery of that pocket. Each pocket has a center situated along a corresponding wafer carrier radial axis. In each of the pockets, a set of bumpers is positioned primarily at a distal portion of the wafer retention pocket opposite the central axis so as to maintain a gap of at least a predefined size between the peripheral wall surface at the distal portion and an edge of a wafer to be placed in the wafer retention pocket.

Abstract: A wafer handing assembly comprising a center hub supporting a vertical non-contact lifting head and at least one radially extending and radially retracting wafer engaging mechanism having a surface to engage a wafer at a peripheral edge of the wafer, where the peripheral edge is a corner edge or a side edge. In some implementations, the wafer engaging mechanism has a foot on which the wafer edge is supported.

Abstract: A wafer handling assembly comprising a center hub supporting a vertical non-contact lifting head and at least one radially extending and radially retracting wafer engaging mechanism having a surface to engage a wafer at a peripheral edge of the wafer, where the peripheral edge is a corner edge or a side edge. In some implementations, the wafer engaging mechanism has a foot on which the wafer edge is supported. The lifting head may be vertically moveable in respect to the assembly.

Abstract: A chemical vapor deposition system is disclosed herein. The chemical vapor deposition system has a plurality of reaction chambers to operate independently in the growth of epitaxial layers on wafers within each of the reaction chambers for the purpose of reducing processing time while maintaining the quality necessary for the fabrication of high-performance semiconductor devices.