Abstract: A system includes a gate formation tool configured to form a sacrificial gate structure and a replacement gate structure, a device dimension measuring tool configured to measure a dimension of the sacrificial gate structure, and a determination unit configured to pick an etching recipe from a series of etching recipes based on the measured dimension of the sacrificial gate structure. The gate formation tool is also configured to partially remove the sacrificial gate structure using the picked etching recipe to form a gate trench for filling the replacement gate structure therein. A portion of the sacrificial gate structure remains in the gate trench, and the series of etching recipes differ at least in a size of the remaining portion of the sacrificial gate structure.

Abstract: The present invention relates to a method of manufacturing gallium nitride quantum dots, and more particularly, to a method of manufacturing gallium nitride quantum dots doped with metal ions, which uses a wet-based synthesis method capable of lowering the fluorescence energy of pure gallium nitride by introducing metal ions into pure gallium nitride.

Abstract: A forming operation method of a resistive random access memory is provided. The method includes the following steps. A positive pulse and a negative pulse are sequentially applied, by a bit line/source line driver, to multiple resistive random access memory cells in a direction form a farthest location to a nearest location based on the bit line/source line driver through a bit line and a source line to break down a dielectric film of each of the resistive random access memory cells and generate a conductive filament of each of the resistive random access memory cells.

Abstract: A waterproof structure of a socket connector includes a waterproof housing, a socket, a cable, and a waterproof plug. The waterproof housing includes a wiring opening. The inner surface of the waterproof housing incudes a ring step surface facing the wiring opening. The wiring opening is covered by an end cap. The socket is received in the waterproof housing. The cable is connected to the socket and passes the wiring opening. The waterproof plug wrapping the cable is arranged in the wiring opening to close the wiring opening. The waterproof plug has an inner and an outer end, the inner end faces the socket, and a longitudinal annular rib is arranged on the inner end. The end cover is fastened to the waterproof housing along the longitudinal direction of the waterproof plug to press the outer end to make the longitudinal ring rib press the ring step surface.

Abstract: The present disclosure describes fabricating devices with tunable gate height and effective capacitance. A method includes forming a first metal gate stack in a dummy region of a semiconductor substrate and a second metal gate stack in an active device region of the semiconductor substrate, and performing a chemical mechanical polishing (CMP) process using a slurry including charged abrasive nanoparticles. The first and second metal gate stacks are different in composition. The charged abrasive nanoparticles include a first concentration in the active device region different from a second concentration in the dummy region.

Abstract: The present invention relates to smart wearable clothing including a stretchable circuit electrode and a smart wearable system, and the smart wearable clothing according to an embodiment of the present invention comprises: a fabric; a stretchable circuit electrode formed on the fabric; a stretchable ACF formed on the circuit electrode; and a chipset formed on the stretchable ACF.

Abstract: A semiconductor structure includes an isolation feature formed in the semiconductor substrate and a first fin-type active region. The first fin-type active region extends in a first direction. A dummy gate stack is disposed on an end region of the first fin-type active region. The dummy, gate stack may overlie an isolation structure. In an embodiment, any recess such as formed for a source/drain region in the first fin-type active region will be displaced from the isolation region by the distance the dummy gate stack overlaps the first fin-type active region.

Abstract: A replaceable electronic device protecting casing includes a front covering pressure plate having an outer frame; a plurality of first screwing holes arranged around the outer frame; a transparent protective film installed in an inner side of a hollow portion of the outer frame; a plurality of second screwing holes arranged around an outer side of the transparent protective film; a waterproof strip attached on an inner side of the transparent protective film; a back seat including a seat body forming a frame body; a plurality of third screwing holes arranged around the frame body; a plurality of screwing units installed in the first screwing holes; and wherein each of the screwing units passes through a respective one first screwing hole, a respective one second screwing hole and a respective one third screwing hole to assemble the front covering pressure plate, the transparent protective film and the back seat.

Abstract: A method includes forming an active region on a substrate, forming a sacrificial gate stack engaging the active region, measuring a gate length of the sacrificial gate stack at a height lower than a top surface of the active region, selecting an etching recipe based on the measured gate length of the sacrificial gate stack, etching the sacrificial gate stack with the etching recipe to form a gate trench, and forming a metal gate stack in the gate trench.

Abstract: Disclosed are various systems that allow for plasma delivery from a central location in a multi-station processing chamber to be redirected to different processing stations within the chamber. Such systems may include a deflector plate that is mounted to a wafer indexer such that the deflector plate is centered on the wafer indexer. In other implementations, such systems may include a deflector plate that is mounted in a fixed relationship with a ceiling of the processing chamber.

Abstract: A method for determining a spam URL includes: (a) extracting a URL from an e-mail; (b) determining whether the extracted URL is a redirecting URL; (c) when the extracted URL is a redirecting URL, accessing a redirection URL that is connected as a result of access to the extracted URL; (d) when the redirection URL is a redirecting URL, accessing a redirection URL that is connected as a result of access to the redirection URL; (e) repeating operation (d); (f) when a last accessed URL in one of operations (c), (d), and (e) is not a redirecting URL, determine whether the last accessed URL is a spam URL; and (g) when it is determined that the last accessed URL is a spam URL, determining the extracted URL, the last accessed URL and any redirection URL connected between the extracted URL and the last accessed URL as spam URLs.

Abstract: An array of programmable memory includes a first floating gate and a second floating gate disposed on a substrate along a first direction, two spacers disposed between and parallel to the first floating gate and the second floating gate, a first word line sandwiched by one of the spacers and the adjacent first floating gate, and a second word line sandwiched by the other one of the spacers and the adjacent second floating gate, and two first spacers disposed on the substrate, wherein one of the first spacer is disposed between the first word line and the first floating gate, and another spacer is disposed between the second word line and the second floating gate, wherein each spacer has substantially the same shape as each first spacer.

Abstract: A semiconductor structure includes a first transistor and a second transistor, and a dielectric structure separating the first transistor from the second transistor. The first transistor includes a first gate structure and the second transistor includes a second gate structure. The dielectric structure includes a first portion sandwiched between the first gate structure and the second gate structure along a first direction, and a second portion protruding from the first portion along a second direction perpendicular to the first direction. The first portion has a first width and the second portion has a second width less than the first width, the first width and the second width being along the first direction, and the first portion has a first height and the second portion has a second height less than the first height.

Abstract: A semiconductor device includes a gate structure, a first doped region, a second doped region, an isolation structure, an insulating layer and a field plate. The gate structure is located on a substrate. The first doped region and the second doped region are located at two sides of the gate structure. The isolation structure is located in the substrate between the first doped region and the second doped region, and is separated from the gate structure by a non-zero distance. The insulating layer extends continuously from a portion of a top surface of the gate structure to a portion of a top surface of the isolation structure. The field plate is located on the insulating layer and has the same potential as the gate structure.

Abstract: SRAM structures are provided. An SRAM structure includes a substrate, a P-type well region over the substrate, an N-type well region over the substrate, a PMOS transistor in the N-type well region, an NMOS transistor in the P-type well region, an isolation region over the boundary between the P-type well region and the N-type well region, and a dielectric structure formed in the isolation region and extending from the isolation region to the boundary between the P-type well region and the N-type well region. The depth of the dielectric structure is greater than that of the isolation region. The PMOS transistor is separated from the NMOS transistor by the isolation region.

Abstract: One or more computer processors determine a runtime feature set for a first container, wherein the runtime feature set includes aggregated temporally collocated container behavior. The one or more computer processors cluster the first container with one or more peer containers or peer pods based on a shared container purpose, similar container behaviors, and similar container file structure. The one or more computer processors determine an additional runtime feature set for each peer container. The one or more computer processors calculate a variance between the first container and each peer container. The one or more computer processors, responsive to the calculated variance exceeding a variance threshold, identify the first container as anomalous.

Abstract: A multifunctional cooling and supporting apparatus for a tablet electronic device comprises a protective case including an upper cover and a lower cover assembled to the upper cover; a hollow space formed between the upper cover and the lower cover; the hollow space serving to accommodate the tablet electronic device; the upper cover having an upper opening; the protective case having a waterproof structure which seals the hollow space and prevents external liquid from penetrating the hollow space; and wherein the upper cover is installed with a heat conducting plate which closes and seals the upper opening of the upper cover; the heat conducting plate has a thermal conductive structure; an outer side of the heat conducting plate is exposed from the upper opening; an inner side of the heat conducting plate serves to contact a back end of the tablet electronic device.

Abstract: In an embodiment, a structure includes: a semiconductor substrate; a gate spacer over the semiconductor substrate, the gate spacer having an upper portion and a lower portion, a first width of the upper portion decreasing continually in a first direction extending away from a top surface of the semiconductor substrate, a second width of the lower portion being constant along the first direction; a gate stack extending along a first sidewall of the gate spacer and the top surface of the semiconductor substrate; and an epitaxial source/drain region adjacent a second sidewall of the gate spacer.

Abstract: A thermoconductive structure includes a waterproof casing, a socket and a thermoconductive plate. The socket is accommodated in the waterproof casing and includes a metal housing having an inserting opening and a side opening defined on a side of the inserting opening. The thermoconductive plate is movably disposed on the metal housing. One surface of the thermoconductive plate protrudes from an inner surface of the metal housing through the side opening. Another surface of the thermoconductive plate is provided with a soft thermoconductive element. The soft thermoconductive element is disposed between an inner surface of the waterproof casing and the thermoconductive plate. When a plug is inserted into the metal housing, the plug pushes the thermoconductive plate to make the soft thermoconductive element be compressed by the thermoconductive plate and the waterproof housing.

Abstract: The present disclosure describes a method of fabricating a semiconductor structure that includes forming a gate structure over a substrate, forming an interlayer dielectric structure surrounding the gate structures, and forming a first opening in the gate structure and the interlayer dielectric structure. The first opening has a first portion in the gate structure and a second portion in the interlayer dielectric structure, in which the first portion has a width larger than the second portion. The method further includes depositing a dielectric layer in the first opening and forming a second opening over the first opening. The first portion of the opening remains open and the second portion of the opening is filled after depositing the dielectric layer. The second opening in the gate structure has a depth larger than the first opening in the gate structure.