Patents by Inventor Yun Chang

Yun Chang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240150730
    Abstract: The present disclosure relates to a novel citrate synthase variant, a microorganism comprising the variant, and a method for producing O-acetyl-L-homoserine and L-methionine using the microorganism.
    Type: Application
    Filed: March 10, 2022
    Publication date: May 9, 2024
    Applicant: CJ CHEILJEDANG CORPORATION
    Inventors: Jin Sook CHANG, Seung Hyun CHO, Seo-Yun KIM, Jaemin LEE, Min Ji BAEK, Imsang LEE
  • Publication number: 20240153786
    Abstract: A method includes bonding a package component to a composite carrier. The composite carrier includes a base carrier and an absorption layer, and the absorption layer is between the base carrier and the package component. A laser beam is projected onto the composite carrier. The laser beam penetrates through the base carrier to ablate the absorption layer. The base carrier may then be separated from the package component.
    Type: Application
    Filed: January 11, 2024
    Publication date: May 9, 2024
    Inventors: Huicheng Chang, Jyh-Cherng Sheu, Chen-Fong Tsai, Yun Chen Teng, Han-De Chen, Yee-Chia Yeo
  • Publication number: 20240148301
    Abstract: The present invention provides a smart wearable device, which is held on an upper body of a wearer by a plurality of contact pad sets, and has a connection unit, a first sensing module, a second sensing module, and an extension unit.
    Type: Application
    Filed: November 7, 2022
    Publication date: May 9, 2024
    Inventors: Chien-Hsiang Chang, Yang-Cheng Lin, Wei-Chih Lien, Tseng-Ping Chiu, Pei-Yun Wu, Bo Liu
  • Patent number: 11978664
    Abstract: A method includes forming a first conductive feature over a semiconductor substrate, forming an ILD layer over the first conductive feature, patterning the ILD layer to form a trench, and forming a conductive layer over the patterned ILD layer to fill the trench. The method further includes polishing the conductive layer to form a via contact configured to interconnect the first conductive feature with a second conductive feature, where polishing the conductive layer exposes a top surface of the ILD layer, polishing the exposed top surface of the ILD layer, such that a top portion of the via contact protrudes from the exposed top surface of the ILD layer, and forming the second conductive feature over the via contact, such that the top portion of the via contact extends into the second conductive feature.
    Type: Grant
    Filed: July 29, 2022
    Date of Patent: May 7, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Pang-Sheng Chang, Chao-Hsun Wang, Kuo-Yi Chao, Fu-Kai Yang, Mei-Yun Wang, Li-Chieh Wu, Chun-Wei Hsu
  • Publication number: 20240145118
    Abstract: A transparent conductor according to an exemplary embodiment of the present invention includes a transparent substrate, and a transparent conductive pattern formed on the transparent substrate, and the transparent conductor includes a nanostructure on an upper surface of at least one of the transparent substrate and the transparent conductive pattern.
    Type: Application
    Filed: March 17, 2021
    Publication date: May 2, 2024
    Inventors: Dae-Guen CHOI, Hyuk Jun KANG, Ji Hye LEE, Junhyuk CHOI, Won Seok CHANG, Joo Yun JUNG, Jun-ho JEONG
  • Patent number: 11973526
    Abstract: An assembly structure for an electronic device protecting casing and an interfacing structure with magnetic connectors includes a protecting casing for protecting a tablet form electronic device and an interfacing device for power or signal transferring to or from the protecting casing. The protecting casing includes a casing side connector. The casing side connector includes an inner connector and an outer connector. The interfacing device includes an interfacing connector. A magnetic connecting device is used for mechanically and magnetically connecting an interfacing connector of the interfacing device with an outer connector of the protecting casing. The magnetic connecting device includes at least one interfacing side magnetic unit which is installed on the interfacing device at the same side installing the interfacing connector, and at least one casing side magnetic unit which is installed one the casing side connector at the same side having the outer connector.
    Type: Grant
    Filed: October 13, 2021
    Date of Patent: April 30, 2024
    Assignee: THE JOY FACTORY, INC.
    Inventors: Sampson Yang, Yun-Chang Tsui
  • Publication number: 20240132904
    Abstract: The present invention relates to a method for producing recombinant human prethrombin-2 protein and having human ?-thrombin activity by the plant-based expression systems.
    Type: Application
    Filed: October 16, 2023
    Publication date: April 25, 2024
    Applicant: PROVIEW-MBD BIOTECH CO., LTD.
    Inventors: Yu-Chia CHANG, Jer-Cheng KUO, Ruey-Chih SU, Li-Kun HUANG, Ya-Yun LIAO, Ching-I LEE, Shao-Kang HUNG
  • Publication number: 20240136291
    Abstract: Semiconductor devices and methods of forming the same are provided. In some embodiments, a method includes receiving a workpiece having a redistribution layer disposed over and electrically coupled to an interconnect structure. In some embodiments, the method further includes patterning the redistribution layer to form a recess between and separating a first conductive feature and a second conductive feature of the redistribution layer, where corners of the first conductive feature and the second conductive feature are defined adjacent to and on either side of the recess. The method further includes depositing a first dielectric layer over the first conductive feature, the second conductive feature, and within the recess. The method further includes depositing a nitride layer over the first dielectric layer. In some examples, the method further includes removing portions of the nitride layer disposed over the corners of the first conductive feature and the second conductive feature.
    Type: Application
    Filed: January 12, 2023
    Publication date: April 25, 2024
    Inventors: Hsiang-Ku SHEN, Chen-Chiu HUANG, Chia-Nan LIN, Man-Yun WU, Wen-Tzu CHEN, Sean YANG, Dian-Hao CHEN, Chi-Hao CHANG, Ching-Wei LIN, Wen-Ling CHANG
  • Patent number: 11966119
    Abstract: An optical film for a display device, includes: a first refractive layer having an upper surface and a lower surface including first projections and second projections extending away from the lower surface in a first direction, the second projections having different heights than the first projections, the first projections having lateral sides with different angles of inclination that decrease in the first direction; and a second refractive layer disposed directly on the upper surface of the first refractive layer, the second refractive layer having a refractive index different from that of the first refractive layer.
    Type: Grant
    Filed: August 28, 2020
    Date of Patent: April 23, 2024
    Assignee: Samsung Display Co., Ltd.
    Inventors: Hye Lim Jang, Young Gu Kim, Ji Yun Park, Jong Ho Son, Jong Min Ok, Sun Young Chang, Baek Kyun Jeon, Kyung Seon Tak
  • Publication number: 20240127892
    Abstract: There are provided a memory device and an operating method of the memory device. The memory device includes: a memory block including a plurality of sub-blocks; a peripheral circuit for performing first program and erase operations in a first manner in a first sub-block, among the plurality of sub-blocks, and performing second program and erase operations in a second manner in a second sub-block, among the plurality of sub-blocks; and a control circuit configured to, when a cycling number of the second program and erase operations that are performed in the second sub-block is equal to or greater than a reference number, control the peripheral circuit to perform a compensation operation that compensates for a threshold voltage of memory cells included in the first sub-block.
    Type: Application
    Filed: April 6, 2023
    Publication date: April 18, 2024
    Applicant: SK hynix Inc.
    Inventors: Dong Uk LEE, Yun Cheol KIM, Hae Chang YANG
  • Patent number: 11963300
    Abstract: A panel device including a substrate, a conductor pad, a turning wire, and a circuit board is provided. The substrate has a first surface and a second surface connected to the first surface while a normal direction of the second surface is different from a normal direction of the first surface. The conductor pad is disposed on the first surface of the substrate. The turning wire is disposed on the substrate and extends from the first surface to the second surface. The turning wire includes a wiring layer in contact with the conductor pad and a wire covering layer covering the wiring layer. The circuit board is bonded to and electrically connected to the wire covering layer. A manufacturing method of a panel device is also provided herein.
    Type: Grant
    Filed: July 9, 2021
    Date of Patent: April 16, 2024
    Assignee: Au Optronics Corporation
    Inventors: Chun-Yueh Hou, Hao-An Chuang, Fan-Yu Chen, Hsi-Hung Chen, Yun Cheng, Wen-Chang Hsieh, Chih-Wen Lu
  • Patent number: 11961775
    Abstract: In one example, a semiconductor device can comprise a substrate, a device stack, first and second internal interconnects, and an encapsulant. The substrate can comprise a first and second substrate sides opposite each other, a substrate outer sidewall between the first substrate side and the second substrate side, and a substrate inner sidewall defining a cavity between the first substrate side and the second substrate side. The device stack can be in the cavity and can comprise a first electronic device, and a second electronic device stacked on the first electronic device. The first internal interconnect can be coupled to the substrate and the device stack. The encapsulant can cover the substrate inner sidewall and the device stack and can fill the cavity. Other examples and related methods are disclosed herein.
    Type: Grant
    Filed: November 8, 2022
    Date of Patent: April 16, 2024
    Assignee: Amkor Technology Singapore Holding Pte. Ltd.
    Inventors: Gyu Wan Han, Won Bae Bang, Ju Hyung Lee, Min Hwa Chang, Dong Joo Park, Jin Young Khim, Jae Yun Kim, Se Hwan Hong, Seung Jae Yu, Shaun Bowers, Gi Tae Lim, Byoung Woo Cho, Myung Jea Choi, Seul Bee Lee, Sang Goo Kang, Kyung Rok Park
  • Publication number: 20240120314
    Abstract: Methods of ion implantation combined with annealing using a pulsed laser or a furnace for cutting substrate in forming semiconductor devices and semiconductor devices including the same are disclosed. In an embodiment, a method includes forming a transistor structure of a device on a first semiconductor substrate; forming a front-side interconnect structure over a front side of the transistor structure; bonding a carrier substrate to the front-side interconnect structure; implanting ions into the first semiconductor substrate to form an implantation region of the first semiconductor substrate; and removing the first semiconductor substrate. Removing the first semiconductor substrate includes applying an annealing process to separate the implantation region from a remainder region of the first semiconductor substrate. The method also includes forming a back-side interconnect structure over a back side of the transistor structure.
    Type: Application
    Filed: December 20, 2023
    Publication date: April 11, 2024
    Inventors: Huicheng Chang, Jyh-Cherng Sheu, Chen-Fong Tsai, Yun Chen Teng, Han-De Chen, Yee-Chia Yeo
  • Patent number: 11951130
    Abstract: The present invention relates to an antigen-binding molecule comprising a heavy chain variable region comprising a heavy-chain complementarity-determining region 1 (HCDR1) comprising an amino acid sequence represented by Sequence No. 1, an HCDR2 comprising an amino acid sequence represented by Sequence No. 2, and an HCDR3 comprising an amino acid sequence represented by Sequence No. 3; a light-chain variable region comprising a light-chain complementarity-determining region 1 (LCDR1) comprising an amino acid sequence represented by Sequence No. 4, an LCDR2 comprising an amino acid sequence represented by Sequence No. 5, and an LCDR3 comprising an amino acid sequence represented by Sequence No. 6; wherein the antigen-binding molecule is a T cell receptor (TCR); and to a cell line expressing the same.
    Type: Grant
    Filed: March 1, 2021
    Date of Patent: April 9, 2024
    Assignee: Eutilex Co., Ltd.
    Inventors: Byoung S. Kwon, Young Ho Kim, Kwang Hee Kim, Ji Won Chung, Young Gyoon Chang, Bo Rim Yi, Jung Yun Lee, Seung Hyun Lee, Sun Woo Im, Jin Kyung Choi, Hyun Tae Son, Eun Hye Yoo
  • Publication number: 20240108727
    Abstract: The present disclosure describes compositions including a eutectic matrix that includes methylsulfonylmethane and a sugar alcohol and particles of a nutraceutical in the eutectic matrix. In some embodiments, the sugar alcohol:methylsulfonylmethane ratio may be from 95:5 to 20:80. Also provided herein are methods for making the compositions and methods for increasing solubility and bioavailability of a nutraceutical.
    Type: Application
    Filed: December 2, 2021
    Publication date: April 4, 2024
    Applicant: InovoBiologic, Inc.
    Inventors: Roland Jacques Gahler, Simon Wood, Chuck Chang, Yun Chai Kuo
  • Publication number: 20240103358
    Abstract: A system includes a mask. The system further includes a pellicle frame attached to the mask. The pellicle frame includes a check valve, wherein the check valve is configured to permit gas flow from a first side of the pellicle from to a second side of the pellicle frame. The pellicle frame further includes a flat bottom surface having only a single recess therein, wherein the flat bottom surface is free of an adhesive. The system further includes a gasket within the single recess.
    Type: Application
    Filed: November 29, 2023
    Publication date: March 28, 2024
    Inventors: Chue San YOO, Hsin-Chang LEE, Pei-Cheng HSU, Yun-Yue LIN
  • Patent number: 11934916
    Abstract: An electronic device includes a pair of depletion gates, an accumulation gate, and a conductive resonator. The depletion gates are spaced apart from each other. The accumulation gate is over the depletion gates. The conductive resonator is over the depletion gates and the accumulation gate. The conductive resonator includes a first portion, a second portion, and a third portion. The first portion and the second portion are on opposite sides of the accumulation gate. The third portion interconnects the first and second portions of the conductive resonator and across the depletion gates. A bottom surface of the first portion of the conductive resonator is lower than a bottom surface of the accumulation gate.
    Type: Grant
    Filed: July 8, 2021
    Date of Patent: March 19, 2024
    Assignees: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD., NATIONAL TAIWAN UNIVERSITY
    Inventors: Jiun-Yun Li, Shih-Yuan Chen, Yao-Chun Chang, Ian Huang, Chiung-Yu Chen
  • Publication number: 20240087891
    Abstract: A method of patterning a substrate includes forming a first line, a second line, and a third line over the substrate, the first line, the second line, and the third line being parallel in a plan view, and forming a fourth line and a fifth line over the first line, the second line, and the third line, the fourth line and the fifth line being orthogonal to the first line in the plan view. The method further includes etching a hole through the second line using the first line, the third line, the fourth line, and the fifth line as an etching mask, and filling the hole with a dielectric material to form a block.
    Type: Application
    Filed: September 13, 2022
    Publication date: March 14, 2024
    Inventors: Eric Chih-Fang Liu, Shihsheng Chang, Kai-Hung Yu, Yun Han
  • Publication number: 20240088208
    Abstract: A method for forming a semiconductor device structure is provided. The method includes forming an interconnect structure over a substrate. The method includes forming a first conductive pad and a mask layer over the interconnect structure. The mask layer covers a top surface of the first conductive pad. The method includes forming a metal oxide layer over a sidewall of the first conductive pad. The method includes forming a second conductive pad over the first conductive pad and passing through the mask layer. The first conductive pad and the second conductive pad are made of different materials.
    Type: Application
    Filed: January 11, 2023
    Publication date: March 14, 2024
    Inventors: Tzu-Ting LIU, Hsiang-Ku SHEN, Wen-Tzu CHEN, Man-Yun WU, Wen-Ling CHANG, Dian-Hau CHEN
  • Patent number: D1025912
    Type: Grant
    Filed: April 19, 2023
    Date of Patent: May 7, 2024
    Inventors: Jianeng Chang, Yun Gao