Abstract: A method for forming a semiconductor device structure is provided. The method includes forming an interconnect structure over a substrate. The method includes forming a first conductive pad and a mask layer over the interconnect structure. The mask layer covers a top surface of the first conductive pad. The method includes forming a metal oxide layer over a sidewall of the first conductive pad. The method includes forming a second conductive pad over the first conductive pad and passing through the mask layer. The first conductive pad and the second conductive pad are made of different materials.

Abstract: An electronic device protecting casing with heating function includes: a casing; a battery box within the casing; an interior of the battery box being arranged with a battery, a back side of the battery box being formed with an opening for receiving the battery; an outer cover serving to seal the opening; an inner side of the outer cover being formed with a heat isolation sheet; a heating unit being installed within the casing for heating the tablet computer; the heating unit including an electric heating plate. When power of the battery is transferred to the electric heating plate, the electric heating plate generates heat power and then transfers the power to the tablet computer for heating it; and a control circuit is installed within the casing; the electric heating plate is connected to the battery through a control switch; and the control circuit is connected to the control switch.

Abstract: A functional safety system of a robot according to an exemplary embodiment of the present disclosure can duplicate modules so as to satisfy a performance level d (pl-d) required for the functional satisfy of a robot.

Abstract: A functional safety system of a robot according to an exemplary embodiment of the present disclosure can generate a safety zone which is a zone to sense whether an obstacle is present.

Abstract: A functional safety system of a robot according to an exemplary embodiment of the present disclosure can duplicate modules so as to satisfy a performance level d (pl-d) required for the functional satisfy of a robot.

Abstract: The present disclosure provides an apparatus for a lithography process in accordance with some embodiments. The apparatus includes a pellicle membrane, a pellicle frame including a material selected from the group consisting of boron nitride (BN), boron carbide (BC), and a combination thereof, a mask, a first adhesive layer that secures the pellicle membrane to the pellicle frame, and a second adhesive layer that secures the pellicle frame to the mask.

Abstract: A device includes a semiconductor fin, a gate structure, gate spacers, and a dielectric feature. The semiconductor fin is over a substrate. The gate structure is over the semiconductor fin and includes a gate dielectric layer over the semiconductor fin and a gate metal covering the gate dielectric layer. The gate spacers are on opposite sides of the gate structure. The dielectric feature is over the substrate. The dielectric feature is in contact with the gate metal, the gate dielectric layer, and the gate spacers, and an interface between the gate metal and the dielectric feature is substantially aligned with an interface between the dielectric feature and one of the gate spacers.

Abstract: The present disclosure relates to a stage-specific process for manufacturing a population of neutrophils, such as chimeric antigen receptor-expressing (CAR-expressing) neutrophils (e.g., T cells and natural killer (NK) cells), from human pluripotent stem cells (hPSCs) using defined media and related compositions, kits, and methods of use (e.g., targeted cancer immunotherapy). Stage-specific processes for generating neutrophils and chimeric antigen receptor (CAR) neutrophils from human pluripotent stem cells (hPSCs) using chemically defined, feeder-free platforms and stage-specific morphogens; cell lines; pharmaceutical compositions; a method of treating cancer; and a kit are within the scopes of this disclosure.

Abstract: Herein disclosed are a surface topography measuring system and a method thereof. The method comprises the following steps: dividing a test beam into a first sub-beam, entering a reflecting mirror along a first axis, and a second sub-beam, entering an object surface along a second axis; moving the reflecting mirror for reflecting the first sub-beam at different positions on the first axis to generate N reflected beams; generating an object reflected beam, related to the second sub-beam, reflected from the object surface; generating N images, related to the N reflected beams and the object reflected beam, and each of the N images having a plurality of interference fringes; analyzing the interference fringes in each of the N images to calculate N curve formulas; calculating a surface topography of the object surface from the N curve formulas.

Abstract: The present disclosure describes fabricating devices with tunable gate height and effective capacitance. A method includes forming a first metal gate stack in a dummy region of a semiconductor substrate and a second metal gate stack in an active device region of the semiconductor substrate, and performing a chemical mechanical polishing (CMP) process using a slurry including charged abrasive nanoparticles. The first and second metal gate stacks are different in composition. The charged abrasive nanoparticles include a first concentration in the active device region different from a second concentration in the dummy region.

Abstract: An array of electrically erasable programmable read only memory (EEPROM) includes a first row of floating gate, a second row of floating gate, two spacers, a first row of word line and a second row of word line. The first row of floating gate and the second row of floating gate are disposed on a substrate along a first direction. The two spacers are disposed between and parallel to the first row of floating gate and the second row of floating gate. The first row of word line is sandwiched by one of the spacers and the adjacent first row of floating gate, and the second row of word line is sandwiched by the other one of the spacers and the adjacent second row of floating gate. The present invention also provides a method of forming said array of electrically erasable programmable read only memory (EEPROM).

Abstract: A semiconductor structure includes a substrate; an isolation structure over the substrate; a first fin extending from the substrate and through the isolation structure; a first source/drain structure over the first fin; a contact etch stop layer over the isolation structure and contacting a first side face of the first source/drain structure; and a first dielectric structure contacting a second side face of the first source/drain structure. The first side face and the second side face are on opposite sides of the first fin in a cross-sectional view cut along a widthwise direction of the first fin. The first dielectric structure extends higher than the first source/drain structure.

Abstract: A ring segment and a turbomachine including the ring segment are provided. The ring segment installed on an inner circumferential surface of a casing and disposed to face an end of a blade existing inside the casing, the ring segment includes a segment body disposed inside the casing in a radial direction of the casing and having a channel through which cooling air flows, and a pair of segment protrusions protruding outward from the segment body, coupled to the inner circumferential surface of the casing, and spaced apart from each other along a flow direction of fluid flowing through the casing to form an RS cavity through which cooling air flows, wherein the segment body includes a cavity for supplying cooling air introduced from the RS cavity to the channel.

Abstract: The present disclosure describes fabricating devices with tunable gate height and effective capacitance. A method includes forming a first metal gate stack in a dummy region of a semiconductor substrate, the first metal gate stack including a first work function metal (WFM) layer; forming a second metal gate stack in an active device region of the semiconductor substrate, the second metal gate stack including a second WFM layer different than the first WFM layer; and performing a CMP process using a slurry including charged abrasive nanoparticles. The charged abrasive nanoparticles include a first concentration in the active device region different from a second concentration in the dummy region causing different polish rates in the active device region and dummy region. After the performing of the CMP process, the first metal gate stack has a first height different from a second height of the second metal gate stack.

Abstract: A method for creating a modified flight simulation program for a flight simulation system includes: obtaining a demonstration flight record associated with a preset track route of a virtual airplane; generating an add-on content pack for the flight simulation program based on the demonstration flight record; and merging the add-on content pack to the flight simulation program to create a modified flight simulation program. The generation of the add-on content pack includes: mapping the preset track route to geographical coordinate data in the real world, creating a first program module associated with a demonstration mode enabling a demonstration virtual flight along the preset track route, creating a second program module associated with an assisted flight mode enabling user control for a virtual flight within a free-flight space, and creating the add-on content pack that includes the first and the second program modules.

Abstract: A method includes forming a fin protruding from a substrate, forming a gate structure across the fin, forming an epitaxial feature over the fin, depositing a dielectric layer covering the epitaxial feature and over sidewalls of the gate structure, performing an etching process to form a trench, the trench dividing the gate structure into first and second gate segments and extending into a region of the dielectric layer, forming a dielectric feature in the trench, recessing a portion of the dielectric feature located in the region, selectively etching the dielectric layer to expose the epitaxial feature, and depositing a conductive feature in physical contact with the epitaxial feature and directly above the portion of the dielectric feature.

Abstract: The present invention relates to compositions comprising factor VIII coagulation factors linked to extended recombinant polypeptide (XTEN), isolated nucleic acids encoding the compositions and vectors and host cells containing the same, and methods of making and using such compositions in treatment of factor VIII-related diseases, disorders, and conditions.

Abstract: A thermoconductive structure includes a waterproof casing, a socket and a thermoconductive plate. The socket is accommodated in the waterproof casing and includes a metal housing having an inserting opening and a side opening defined on a side of the inserting opening. The thermoconductive plate is movably disposed on the metal housing. One surface of the thermoconductive plate protrudes from an inner surface of the metal housing through the side opening. Another surface of the thermoconductive plate is provided with a soft thermoconductive element. The soft thermoconductive element is disposed between an inner surface of the waterproof casing and the thermoconductive plate. When a plug is inserted into the metal housing, the plug pushes the thermoconductive plate to make the soft thermoconductive element be compressed by the thermoconductive plate and the waterproof housing.

Abstract: A waterproof structure of a socket connector includes a waterproof housing, a socket, a cable, and a waterproof plug. The waterproof housing includes a wiring opening. The inner surface of the waterproof housing incudes a ring step surface facing the wiring opening. The wiring opening is covered by an end cap. The socket is received in the waterproof housing. The cable is connected to the socket and passes the wiring opening. The waterproof plug wrapping the cable is arranged in the wiring opening to close the wiring opening. The waterproof plug has an inner and an outer end, the inner end faces the socket, and a longitudinal annular rib is arranged on the inner end. The end cover is fastened to the waterproof housing along the longitudinal direction of the waterproof plug to press the outer end to make the longitudinal ring rib press the ring step surface.

Abstract: An array of programmable memory includes a first floating gate and a second floating gate disposed on a substrate along a first direction, two spacers disposed between and parallel to the first floating gate and the second floating gate, a first word line sandwiched by one of the spacers and the adjacent first floating gate, and a second word line sandwiched by the other one of the spacers and the adjacent second floating gate, and two first spacers disposed on the substrate, wherein one of the first spacer is disposed between the first word line and the first floating gate, and another spacer is disposed between the second word line and the second floating gate, wherein each spacer has substantially the same shape as each first spacer.