Abstract: A solar cell module includes a solar cell, a front protection plate disposed on a front side of the solar cell, and protrusions and depressions formed on a surface of the front protection plate, wherein the protrusions and depressions have a pitch equal to or less than a wavelength of visible light.

Abstract: A solar cell module includes a plurality of solar cells connected to each other, each solar cell of the plurality of solar cells independently includes a semiconductor substrate, one n+ region and one p+ region disposed on one side of the semiconductor substrate and separated from each other, at least one first electrode and at least one second electrode, in which the at least one first electrode is electrically connected to the n+ region and the at least one second electrode is electrically connected to the p+ region, and a first trench and a second trench disposed on each of the plurality of solar cells, wherein the first trench is disposed on the one side of the semiconductor substrate and the second trench is disposed on the other opposite facing side of the semiconductor substrate, the first and second trenches are separated from each other.

Abstract: Solar cells include a substrate having a light collecting surface thereon and a P-N rectifying junction within the substrate. The P-N rectifying junction includes a base region of first conductivity type (e.g., p-type) and a semiconductor layer of second conductivity type extending between the base region and the light collecting surface. A trench is also provided, which extends through the semiconductor layer and into the base region. First and second electrodes are provided adjacent the light collecting surface. The first electrode is electrically coupled to the semiconductor layer and the second electrode is electrically coupled to the base region, at a location adjacent a bottom of the trench.

Abstract: A non-volatile memory device for 2-bit operation and a method of fabricating the same are provided. The non-volatile memory device includes an active region and a gate extending in a word line direction on a semiconductor substrate, and crossing each other repeatedly; a charge storage layer disposed below the gate, and confined at a portion where the gate and the active region cross; a charge blocking layer formed on the charge storage layer; a tunnel dielectric layer formed below the charge storage layer; first and second source/drain regions formed in the active region exposed by the gate; and first and second bit lines crossing the word line direction. The active region may be formed in a first zigzag pattern and/or the gate may be formed in a second zigzag pattern in symmetry with the first zigzag pattern.

Abstract: A non-volatile memory device for 2-bit operation and a method of fabricating the same are provided. The non-volatile memory device includes an active region and a gate extending in a word line direction on a semiconductor substrate, and crossing each other repeatedly; a charge storage layer disposed below the gate, and confined at a portion where the gate and the active region cross; a charge blocking layer formed on the charge storage layer; a tunnel dielectric layer formed below the charge storage layer; first and second source/drain regions formed in the active region exposed by the gate; and first and second bit lines crossing the word line direction. The active region may be formed in a first zigzag pattern and/or the gate may be formed in a second zigzag pattern in symmetry with the first zigzag pattern.

Abstract: A non-volatile memory device for 2-bit operation and a method of fabricating the same are provided. The non-volatile memory device includes an active region and a gate extending in a word line direction on a semiconductor substrate, and crossing each other repeatedly; a charge storage layer disposed below the gate, and confined at a portion where the gate and the active region cross; a charge blocking layer formed on the charge storage layer; a tunnel dielectric layer formed below the charge storage layer; first and second source/drain regions formed in the active region exposed by the gate; and first and second bit lines crossing the word line direction. The active region may be formed in a first zigzag pattern and/or the gate may be formed in a second zigzag pattern in symmetry with the first zigzag pattern.

Abstract: Disclosed herein is a plasma display panel in which afterimage is improved. The plasma display panel according to the present invention includes a panel unit having an upper plate and a lower plate, a frame that supports circuitry, and a conductive material formed between the panel unit and the frame. As such, a conductive material is formed on a bottom surface of a lower plate of a panel. Thus, charges introduced into the lower plate are properly controlled to improve the waveform stability of the panel. Also, a charge characteristic is improved to implement a stable operation. Accordingly, an afterimage time can be reduced. Further, a sheet of a low hardness and light weight is used. It is thus possible to absorb shock and noise of a PDP, accomplish light weight of the PDP and reduce the materials of the sheet.

Abstract: A non-volatile memory device for 2-bit operation and a method of fabricating the same are provided. The non-volatile memory device includes an active region and a gate extending in a word line direction on a semiconductor substrate, and crossing each other repeatedly; a charge storage layer disposed below the gate, and confined at a portion where the gate and the active region cross; a charge blocking layer formed on the charge storage layer; a tunnel dielectric layer formed below the charge storage layer; first and second source/drain regions formed in the active region exposed by the gate; and first and second bit lines crossing the word line direction. The active region may be formed in a first zigzag pattern and/or the gate may be formed in a second zigzag pattern in symmetry with the first zigzag pattern.

Abstract: A solar cell is provided with a semiconductor substrate including a light-receiving surface, a back surface, a first region of a first conductivity type disposed on the back surface, a second region of a second conductivity type disposed on the light-receiving surface, and a PN junction at the boundary between the first and second regions. An electrode is provided on the light-receiving surface to expose a portion of the light-receiving surface, and the semiconductor substrate includes a plurality of recesses formed by recessing the exposed portion of the light-receiving surface. The recesses may function as a texturing structure.

Abstract: A non-volatile memory device for 2-bit operation and a method of fabricating the same are provided. The non-volatile memory device includes an active region and a gate extending in a word line direction on a semiconductor substrate, and crossing each other repeatedly; a charge storage layer disposed below the gate, and confined at a portion where the gate and the active region cross; a charge blocking layer formed on the charge storage layer; a tunnel dielectric layer formed below the charge storage layer; first and second source/drain regions formed in the active region exposed by the gate; and first and second bit lines crossing the word line direction. The active region may be formed in a first zigzag pattern and/or the gate may be formed in a second zigzag pattern in symmetry with the first zigzag pattern.

Abstract: An integrated circuit device includes a substrate including a trench therein and a conductive plug wire pattern in the trench. The conductive plug wire pattern includes a recessed portion that exposes portions of opposing sidewalls of the trench, and an integral plug portion that protrudes from a surface of the recessed portion to provide an electrical connection to at least one other conductive wire pattern on a different level of metallization. A surface of the plug portion may protrude to a substantially same level as a surface of the substrate adjacent to and outside the trench, and the surface of the recessed portion may be below the surface of the substrate outside the trench. Related fabrication methods are also discussed.

Abstract: A plasma display apparatus is provided. The plasma display apparatus includes an upper substrate, a lower substrate that faces the upper substrate, and barrier ribs formed on the lower substrate to partition off discharge cells. At least one groove having a width no less than 0.1 times and no more than 0.8 times the width of the barrier rib is formed on the barrier rib. Therefore, it is possible to reduce a capacitance value between address electrodes and reduce reactive power formed between the electrodes so that it is possible to improve the discharge efficiency of the panel.

Abstract: Provided is a solar cell module having improved energy efficiency. The solar cell module includes a frame, first solar cells arranged at the frame, and second solar cells smaller than the first solar cells. The second solar cells are disposed in regions surrounded by the first solar cells. The first solar cells have a substantially circular shape. The second solar cells have a rectangular shape, and each of the second solar cells is surrounded by four of the first solar cells.

Abstract: In one embodiment, a semiconductor device has an active region defined by an isolation layer formed inside an STI trench that includes an upper trench and a lower trench having a substantially curved cross-sectional profile under the upper trench so that the lower trench is in communication with the upper trench. Since the upper trench has a sidewall tapered with a positive slope, a good gap filling property can be obtained when filling the upper trench with an insulating layer. By forming a void in the lower trench, a dielectric constant at the bottom of the isolation layer is lower than a dielectric constant at an oxide layer, thereby improving the isolation property. The isolation layer includes a first insulating layer formed inside only the upper trench and covering an inner wall of the upper trench in the form of a spacer.

Abstract: Solar cells include a substrate having a light collecting surface thereon and a P-N rectifying junction within the substrate. The P-N rectifying junction includes a base region of first conductivity type (e.g., p-type) and a semiconductor layer of second conductivity type extending between the base region and the light collecting surface. A trench is also provided, which extends through the semiconductor layer and into the base region. First and second electrodes are provided adjacent the light collecting surface. The first electrode is electrically coupled to the semiconductor layer and the second electrode is electrically coupled to the base region, at a location adjacent a bottom of the trench.

Abstract: Solar cells include a substrate having a light collecting surface thereon and a P-N rectifying junction within the substrate. The P-N rectifying junction includes a base region of first conductivity type (e.g., p-type) and a semiconductor layer of second conductivity type extending between the base region and the light collecting surface. A trench is also provided, which extends through the semiconductor layer and into the base region. First and second electrodes are provided adjacent the light collecting surface. The first electrode is electrically coupled to the semiconductor layer and the second electrode is electrically coupled to the base region, at a location adjacent a bottom of the trench.

Abstract: A plasma display panel includes scan electrode lines, sustain electrode lines and data electrode lines formed within a display area. A common electrode line is formed along a side of the device at a non-display area and is commonly connected to the sustain electrode lines. A first pad portion is formed at a non-display area on a side of the device, and wires carrying scan signals are connected to the scan electrode lines at the first pad portion. A second pad portion is also formed at a non-display area on either a side edge, an upper edge or a bottom edge of the device, and a conductive path carries a sustain signal to the common line through the second pad portion.

Abstract: A plasma display panel is provided that has an inter-electrode distance in a structure where a black layer and an electrode are separated from each other. The plasma display apparatus may have the effect that reactive current is reduced by lowering capacitance. Further, the plasma display panel may have the effect that emission of light by discharge is smoothly performed by controlling a width of an upper and lower portion of a second barrier rib and a width of the first barrier rib according to the width of the upper portion of the second barrier rib such that a luminance can be increased and interference of adjacent cells can be minimized. This may have an effect that a sustain period where an image is displayed can be secured relatively longer since an address time during which the scan pulse is applied is reduced.

Abstract: An ink-jet printhead and a method of manufacturing the same include a substrate on which a heater and a passivation layer protecting the heater are formed, a passage plate on which an ink chamber corresponding to the heater and an ink passage connected to the ink chamber are formed, and a nozzle plate in which an orifice corresponding to the ink chamber is formed. An exposure stop layer (ESL) that blocks passage of a photosensitive energy is formed inside the nozzle plate, and the nozzle plate and the passage plate are bonded with each other by the exposure stop layer (ESL).

Abstract: A semiconductor device capable of suppressing void migration is provided. The semiconductor device includes a dummy region extending in a first direction substantially perpendicular to a second direction in which a word line extends. In addition, an isolation layer pattern may not cut the dummy region in the second direction. Consequently, leaning of the dummy region and void migration are prevented. A method of fabricating the semiconductor device is also provided.