Abstract: A vertical type nanotuhe semiconductor device including a nanotube bit line, disposed on a substrate and in parallel with the substrate and composed of a nanotube with a conductive property, and a nanotube pole connected to the bit line vertically to the substrate and provides a channel through which carriers migrate. By manufacturing the semiconductor device using the bit line composed of the nanotube, cutoff of an electrical connection of the bit line is prevented and an integration density of the semiconductor device can be improved.

Abstract: Provided are transistors, semiconductor integrated circuit interconnections and methods of forming the same. The transistors, semiconductor integrated circuit interconnections and methods of forming the same may improve electrical characteristics between gate electrodes or interconnection electrodes and simplify a semiconductor fabrication process related to gate electrodes or interconnection electrodes. A material layer having first and second regions may be prepared. A trench may be formed in a selected portion of the first region. Transistors or semiconductor integrated circuit interconnections may be in the first and second regions, respectively. One of the transistors or the semiconductor integrated circuit interconnections may be formed in the trench. The transistors or the semiconductor integrated circuit interconnections may be electrically insulated from each other.

Abstract: A vertical type nanotube semiconductor device including a nanotube bit line, disposed on a substrate and in parallel with the substrate and composed of a nanotube with a conductive property, and a nanotube pole connected to the bit line vertically to the substrate and provides a channel through which carriers migrate. By manufacturing the semiconductor device using the bit line composed of the nanotube, cutoff of an electrical connection of the bit line is prevented and an integration density of the semiconductor device can be improved.

Abstract: A bubble-ink jet print head includes: a substrate having ink chambers to store ink and resistance heat emitting bodies to heat ink disposed thereover; and an ink supply passage which penetrates the substrate and which is connected with the ink chambers. The ink supply passage includes: a first trench formed at a first surface of the substrate in a first pattern having a separating distance from at least one of inlets of the ink chambers and connecting portions between the adjacent ink chambers, the first surface of the substrate having the ink chambers disposed thereover, and a second trench formed at a second surface of the substrate in a second pattern, having one of an area equal to and an area smaller than that of the first trench in the range of the first pattern of the first trench, and in communication with the first trench.

Abstract: Provided are transistors, semiconductor integrated circuit interconnections and methods of forming the same. The transistors, semiconductor integrated circuit interconnections and methods of forming the same may improve electrical characteristics between gate electrodes or interconnection electrodes and simplify a semiconductor fabrication process related to gate electrodes or interconnection electrodes. A material layer having first and second regions may be prepared. A trench may be formed in a selected portion of the first region. Transistors or semiconductor integrated circuit interconnections may be in the first and second regions, respectively. One of the transistors or the semiconductor integrated circuit interconnections may be formed in the trench. The transistors or the semiconductor integrated circuit interconnections may be electrically insulated from each other.

Abstract: A semiconductor device includes a semiconductor substrate having a cell region and a peripheral circuit region defined therein. A buried word line is disposed in the substrate in the cell region and has a top surface lower than top surfaces of cell active regions in the cell region. A gate line is disposed on the substrate in the peripheral circuit region. A word line interconnect is disposed in the substrate in the peripheral circuit region, the word line interconnect including a first portion contacting the buried word line and having a top surface lower than a top surfaces of the cell active regions and a second portion that is overlapped by and in contact with the gate line.

Abstract: A semiconductor device capable of suppressing void migration is provided. The semiconductor device includes a dummy region extending in a first direction substantially perpendicular to a second direction in which a word line extends. In addition, an isolation layer pattern may not cut the dummy region in the second direction. Consequently, leaning of the dummy region and void migration are prevented. A method of fabricating the semiconductor device is also provided.

Abstract: Methods of fabricating semiconductor devices capable of maintaining a liner on both sidewalls of an active region overlapping a gate are provided. An isolation trench defining an active region is formed in a semiconductor substrate. A liner is formed on sidewalls of the active region. An isolation layer filling the isolation trench is formed. A hard mask pattern is formed on the semiconductor substrate having the liner and the isolation layer. A gate trench crossing the active region is formed using the hard mask pattern as an etching mask. A gate is formed in the gate trench. After forming the gate, the hard mask pattern is removed. A gate capping pattern is formed on the gate.

Abstract: A bubble-ink jet print head includes: a substrate having ink chambers to store ink and resistance heat emitting bodies to heat ink disposed thereover; and an ink supply passage which penetrates the substrate and which is connected with the ink chambers. The ink supply passage includes: a first trench formed at a first surface of the substrate in a first pattern having a separating distance from at least one of inlets of the ink chambers and connecting portions between the adjacent ink chambers, the first surface of the substrate having the ink chambers disposed thereover, and a second trench formed at a second surface of the substrate in a second pattern, having one of an area equal to and an area smaller than that of the first trench in the range of the first pattern of the first trench, and in communication with the first trench.

Abstract: A semiconductor device capable of suppressing void migration is provided. The semiconductor device includes a dummy region extending in a first direction substantially perpendicular to a second direction in which a word line extends. In addition, an isolation layer pattern may not cut the dummy region in the second direction. Consequently, leaning of the dummy region and void migration are prevented. A method of fabricating the semiconductor device is also provided.

Abstract: A bubble-ink jet print head includes: a substrate having ink chambers to store ink and resistance heat emitting bodies to heat ink disposed thereover; and an ink supply passage which penetrates the substrate and which is connected with the ink chambers. The ink supply passage includes: a first trench formed at a first surface of the substrate in a first pattern having a separating distance from at least one of inlets of the ink chambers and connecting portions between the adjacent ink chambers, the first surface of the substrate having the ink chambers disposed thereover, and a second trench formed at a second surface of the substrate in a second pattern, having one of an area equal to and an area smaller than that of the first trench in the range of the first pattern of the first trench, and in communication with the first trench.

Abstract: A plasma display apparatus is provided. The plasma display apparatus includes an upper substrate, a lower substrate that faces the upper substrate, and barrier ribs formed on the lower substrate to partition off discharge cells. At least one groove having a width no less than 0.1 times and no more than 0.8 times the width of the barrier rib is formed on the barrier rib. Therefore, it is possible to reduce a capacitance value between address electrodes and reduce reactive power formed between the electrodes so that it is possible to improve the discharge efficiency of the panel.

Abstract: A semiconductor device capable of suppressing void migration is provided. The semiconductor device includes a dummy region extending in a first direction substantially perpendicular to a second direction in which a word line extends. In addition, an isolation layer pattern may not cut the dummy region in the second direction. Consequently, leaning of the dummy region and void migration are prevented. A method of fabricating the semiconductor device is also provided.

Abstract: In one embodiment, a semiconductor device has an active region defined by an isolation layer formed inside an STI trench that includes an upper trench and a lower trench having a substantially curved cross-sectional profile under the upper trench so that the lower trench is in communication with the upper trench. Since the upper trench has a sidewall tapered with a positive slope, a good gap filling property can be obtained when filling the upper trench with an insulating layer. By forming a void in the lower trench, a dielectric constant at the bottom of the isolation layer is lower than a dielectric constant at an oxide layer, thereby improving the isolation property. The isolation layer includes a first insulating layer formed inside only the upper trench and covering an inner wall of the upper trench in the form of a spacer.

Abstract: A vertical type nanotube semiconductor device including a nanotube bit line, disposed on a substrate and in parallel with the substrate and composed of a nanotube with a conductive property, and a nanotube pole connected to the bit line vertically to the substrate and provides a channel through which carriers migrate. By manufacturing the semiconductor device using the bit line composed of the nanotube, cutoff of an electrical connection of the bit line is prevented and an integration density of the semiconductor device can be improved.

Abstract: A non-volatile memory device for 2-bit operation and a method of fabricating the same are provided. The non-volatile memory device includes an active region and a gate extending in a word line direction on a semiconductor substrate, and crossing each other repeatedly; a charge storage layer disposed below the gate, and confined at a portion where the gate and the active region cross; a charge blocking layer formed on the charge storage layer; a tunnel dielectric layer formed below the charge storage layer; first and second source/drain regions formed in the active region exposed by the gate; and first and second bit lines crossing the word line direction. The active region may be formed in a first zigzag pattern and/or the gate may be formed in a second zigzag pattern in symmetry with the first zigzag pattern.

Abstract: An ink-jet printhead, and a method for manufacturing the same. The printhead includes a substrate, a first insulating layer on the surface of the substrate, first and second conductors on the first insulating layer separated from each other, a heater including conductor connection layers for electrically connecting the first and second conductors to each other and between the first and second conductors. A second insulating layer is between the first and second conductors and between the conductor connection layers, and a barrier wall is provided on the substrate and defines an ink chamber filled with ink to be ejected. A nozzle plate is provided on the barrier wall, and forms upper walls of the ink chamber and in which nozzles, through which ink filled in the ink chamber is ejected, are formed.

Abstract: Methods of forming integrated circuit devices (e.g., memory devices) include the use of preferred self-aligned contact hole fabrication steps. These steps improve process reliability by reducing the likelihood that contact holes will become misaligned to underlying integrated circuit device structures and thereby potentially expose the structures in an adverse manner. Typical methods include the steps of forming a plurality of interconnection patterns on a substrate and then covering a surface of the interconnection patterns and a portion of the substrate with a capping insulating layer such as silicon nitride layer. The capping insulating layer is then covered with an upper interlayer insulating layer different from the capping insulating layer. The upper interlayer insulating layer and the capping insulating layer are then dry-etched in sequence to form a first narrow contact hole that exposes the substrate, but preferably does not expose the interconnection patterns.

Abstract: An ink-jet printhead and a method of manufacturing the ink-jet printhead include a substrate on which at least one heater and a passivation layer protecting the at least one heater are formed, a passage plate formed on the substrate to provide a chamber corresponding to the at least one heater, and a nozzle plate in which an orifice corresponding to the chamber is formed. The passage plate is formed of photoresist, and the nozzle plate is formed of a silicon-family material at a temperature limited by characteristics of the passage plate.

Abstract: An ink-jet printhead and a method of manufacturing the ink-jet printhead include forming an insulating layer on a surface of a substrate, forming a metallic thin layer on the insulating layer, pattering the metallic thin layer through dry etching to form a plurality of pairs of conductors corresponding to a plurality of heaters to be formed in a subsequent operation, forming a resistant material layer on the substrate, patterning the resistant material layer through dry etching to form the heaters corresponding to the conductors, forming a nonconductive heat transfer layer on the substrate so as to cover the heaters and the conductors, forming a passage plate providing an ink chamber, in which each of the heaters are placed, on the substrate, and forming a nozzle plate having a nozzle corresponding to each ink chamber on the passage plate.