Abstract: An ink-jet printhead and a method of manufacturing the same include utilizing a substrate on which at least one heater and a passivation layer protecting the at least one heater are formed, a passage plate which forms an ink chamber corresponding to the at least one heater, and a nozzle plate in which an orifice corresponding to the ink chamber is formed. The passage plate and the nozzle plate are formed of photoresist, and an adhesion layer formed of silicon-family low-temperature deposition material at a temperature limited by the characteristics of the passage plate is disposed between the passage plate and the nozzle plate.

Abstract: In a heater apparatus of an ink-jet print head and a fabrication method thereof, heaters and/or wires are formed to have a dopant doped therein by an ion implantation process carried out to regulate a resistance of the heaters and/or the wires, after forming the wire/heater pattern having the heaters and the wires with an electric conductor layer. Alternatively, the heaters and the wires can be formed of a heater pattern and a wire pattern respectively made of a heater layer and a wire layer, instead of forming the wire/resistance heat emitting body pattern with an electric conductor layer.

Abstract: A bubble-ink jet print head includes: a substrate having ink chambers to store ink and resistance heat emitting bodies to heat ink disposed thereover; and an ink supply passage which penetrates the substrate and which is connected with the ink chambers. The ink supply passage includes: a first trench formed at a first surface of the substrate in a first pattern having a separating distance from at least one of inlets of the ink chambers and connecting portions between the adjacent ink chambers, the first surface of the substrate having the ink chambers disposed thereover, and a second trench formed at a second surface of the substrate in a second pattern, having one of an area equal to and an area smaller than that of the first trench in the range of the first pattern of the first trench, and in communication with the first trench.

Abstract: An ink-jet printhead, and a method for manufacturing the same. The printhead includes a substrate, a first insulating layer on the surface of the substrate, first and second conductors on the first insulating layer separated from each other, a heater including conductor connection layers for electrically connecting the first and second conductors to each other and between the first and second conductors. A second insulating layer is between the first and second conductors and between the conductor connection layers, and a barrier wall is provided on the substrate and defines an ink chamber filled with ink to be ejected. A nozzle plate is provided on the barrier wall, and forms upper walls of the ink chamber and in which nozzles, through which ink filled in the ink chamber is ejected, are formed.

Abstract: Methods of forming integrated circuit devices (e.g., memory devices) include the use of preferred self-aligned contact hole fabrication steps. These steps improve process reliability by reducing the likelihood that contact holes will become misaligned to underlying integrated circuit device structures and thereby potentially expose the structures in an adverse manner. Typical methods include the steps of forming a plurality of interconnection patterns on a substrate and then covering a surface of the interconnection patterns and a portion of the substrate with a capping insulating layer such as silicon nitride layer. The capping insulating layer is then covered with an upper interlayer insulating layer different from the capping insulating layer. The upper interlayer insulating layer and the capping insulating layer are then dry-etched in sequence to form a first narrow contact hole that exposes the substrate, but preferably does not expose the interconnection patterns.

Abstract: An ink-jet printhead and a method of manufacturing the same include a substrate on which a heater and a passivation layer protecting the heater are formed, a passage plate on which an ink chamber corresponding to the heater and an ink passage connected to the ink chamber are formed, and a nozzle plate in which an orifice corresponding to the ink chamber is formed. An exposure stop layer (ESL) that blocks passage of a photosensitive energy is formed inside the nozzle plate, and the nozzle plate and the passage plate are bonded with each other by the exposure stop layer (ESL).

Abstract: An ink-jet printhead and a method of manufacturing the same include utilizing a substrate on which at least one heater and a passivation layer protecting the at least one heater are formed, a passage plate which forms an ink chamber corresponding to the at least one heater, and a nozzle plate in which an orifice corresponding to the ink chamber is formed. The passage plate and the nozzle plate are formed of photoresist, and an adhesion layer formed of silicon-family low-temperature deposition material at a temperature limited by the characteristics of the passage plate is disposed between the passage plate and the nozzle plate.

Abstract: An ink-jet printhead and a method of manufacturing the ink-jet printhead include forming an insulating layer on a surface of a substrate, forming a metallic thin layer on the insulating layer, pattering the metallic thin layer through dry etching to form a plurality of pairs of conductors corresponding to a plurality of heaters to be formed in a subsequent operation, forming a resistant material layer on the substrate, patterning the resistant material layer through dry etching to form the heaters corresponding to the conductors, forming a nonconductive heat transfer layer on the substrate so as to cover the heaters and the conductors, forming a passage plate providing an ink chamber, in which each of the heaters are placed, on the substrate, and forming a nozzle plate having a nozzle corresponding to each ink chamber on the passage plate.

Abstract: An ink-jet printhead and a method of manufacturing the ink-jet printhead include a substrate on which at least one heater and a passivation layer protecting the at least one heater are formed, a passage plate formed on the substrate to provide a chamber corresponding to the at least one heater, and a nozzle plate in which an orifice corresponding to the chamber is formed. The passage plate is formed of photoresist, and the nozzle plate is formed of a silicon-family material at a temperature limited by characteristics of the passage plate.

Abstract: Methods of forming integrated circuit devices (e.g., memory devices) include the use of preferred self-aligned contact hole fabrication steps. These steps improve process reliability by reducing the likelihood that contact holes will become misaligned to underlying integrated circuit device structures and thereby potentially expose the structures in an adverse manner. Typical methods include the steps of forming a plurality of interconnection patterns on a substrate and then covering a surface of the interconnection patterns and a portion of the substrate with a capping insulating layer such as silicon nitride layer. The capping insulating layer is then covered with an upper interlayer insulating layer different from the capping insulating layer. The upper interlayer insulating layer and the capping insulating layer are then dry-etched in sequence to form a first narrow contact hole that exposes the substrate, but preferably does not expose the interconnection patterns.

Abstract: A method for fabricating a cylindrical capacitor that exceeds photolithographic resolution. The capacitor is formed by partially etching the storage node opening, thereby reducing the distance between adjacent openings defined by the photolithographic process. The openings defined by the photolithographic process is enlarged by wet etching the sidewalls of the openings by at least the same thickness as that of a subsequently formed conductive layer for storage node formation. Contact plugs that are electrically connected to the bottom of the cylindrical storage nodes protrude from the top surface of an insulating layer in order to increase process margins and decrease contact resistance.

Abstract: A method for fabricating a SOI semiconductor device including providing a semiconductor substrate; forming a device isolation layer in and on a first surface of the semiconductor substrate to define an active region, including a source/drain region, and an inactive region; forming a first gate electrode on the first surface of the substrate; forming a first insulating layer on the first gate electrode; forming a capacitor, electrically connected to the source/drain region, on the first insulating layer; forming a second insulating layer on the capacitor; forming a third insulating layer on the second surface of the substrate; forming a body contact conductor line, electrically connected to the active region of substrate, on and through the third insulating layer; forming a fourth insulating layer on the body contact conductor line; and forming a bit line on the fourth insulating layer to be electrically connected to the source/drain region of the substrate.

Abstract: A silicon on insulator transistor including a gate electrode, a pair of source/drain regions and a channel area is electrically connected to a conductor through an opening in an insulating layer formed therebetween, through the channel area. The presence of the conductor prevents irregular variation in threshold voltage and reduces the sub-threshold leakage and thereby guarantees high operating speed. A transistor including a pair of source/drain regions and a channel area is formed on one surface of a semiconductor substrate or processing wafer. A first insulating layer is formed on the transistor and over the semiconductor substrate/processing wafer. A handling wafer is bonded onto the first insulating layer. The other surface of the semiconductor substrate/processing wafer is ground and/or polished. A second insulating layer is formed on the ground/polished semiconductor substrate/processing wafer.

Abstract: A SOI semiconductor device including a substrate, a first gate electrode formed on a first surface of the substrate between a source/drain region, a first insulating layer formed on the first gate electrode and the first surface of the substrate, a capacitor formed on the first insulating layer, electrically connected to the source/drain region, a second insulating layer formed on the capacitor and the first insulating layer, a third insulating layer formed on a second surface of the substrate, a body contact conductor line formed on and through the third insulating layer in alignment with the first gate electrode, electrically connected to the substrate aligned with the first gate electrode between the source/drain region, a fourth insulating layer formed on the body contact conductor line and the third insulating layer, and a bit line formed on the fourth insulating layer, electrically connected to the source/drain region of the substrate.

Abstract: A method for fabricating a cylindrical capacitor that exceeds photolithographic resolution. The capacitor is formed by partially etching the storage node opening, thereby reducing the distance between adjacent openings defined by the photolithographic process. The openings defined by the photolithographic process is enlarged by wet etching the sidewalls of the openings by at least the same thickness as that of a subsequently formed conductive layer for storage node formation. Contact plugs that are electrically connected to the bottom of the cylindrical storage nodes protrude from the top surface of an insulating layer in order to increase process margins and decrease contact resistance.

Abstract: A method of forming a contact for a dynamic random access memory device is disclosed. In this method, a first insulating layer is formed on a semiconductor substrate. First and second contact pads are formed in the first insulating layer and on a semiconductor substrate in such a manner that a top surface of the first insulating layer is higher than top surfaces of the contact pads. Then a second insulating layer is formed over the substrate, which layer shows a bad step coverage. The second insulating layer is etched until the surfaces of the first and second contact pads are exposed. Then a first conductive layer is formed over the entire surface of the semiconductor substrate, and the first conductive layer is flattened, leaving some thickness of the second insulating layer. Then a second conductive layer is formed over the first conductive layer, and the second and first conductive layers are sequentially etched using a bit line forming mask, to form a bit line.

Abstract: Methods of forming semiconductor substrates include the steps of bonding a first semiconductor substrate to a second semiconductor substrate. The first semiconductor substrate has a first adhesion layer thereon extending opposite a first surface thereof and a first diffusion barrier layer extending between the first adhesion layer and the first surface. The second semiconductor substrate has a second adhesion layer thereon. The first diffusion barrier layer prevents impurities from within the first adhesion layer from diffusing directly into the first semiconductor substrate during subsequent thermal treatment steps (e.g., annealing). A second diffusion barrier layer is then formed to encapsulate the bonded wafers and the adhesion layers and diffusion barrier layer therebetween. The second diffusion barrier layer prevents impurities from within the adhesion layers from out-diffusing (from the lateral edges of the adhesion layers) during the subsequent thermal treatment steps (e.g., annealing steps).

Abstract: Contacts to a cell area and to a core area of integrated circuit memory devices are fabricated by forming a first interlayer dielectric layer on the cell area and on the core area, including on a plurality of spaced apart insulated gates in the cell area. The first interlayer dielectric layer includes therein a plurality of first contact holes having sidewalls that extend from a face of the first interlayer dielectric layer through the first interlayer dielectric layer. The first contact holes further extend between the plurality of spaced apart insulated gates. A first recessed conductive layer is formed in the plurality of first contact holes, between the plurality of spaced apart insulating gates, and recessed beneath the face of the first interlayer dielectric layer. A second dielectric layer then is conformally formed on the face of the first dielectric layer, on the sidewalls of the first contact holes and on the first recessed conductive layer in the first contact holes.

Abstract: A memory cell is formed including an insulation region on the substrate and a transistor including a gate on the substrate and a source/drain region in the substrate disposed between the gate and the insulation region. The cell also includes a capacitor including an electrode overlying the insulation region, the electrode having a lateral surface adjacent the source/drain region. A conductive interconnecting region is formed on the substrate and extends from the source/drain region to contact the lateral surface of the first electrode of the capacitor. The capacitor may include a first electrode on the insulation region, a dielectric region on the first electrode, and a second electrode on the dielectric region. The first electrode preferably is platinum and the dielectric region preferably is a ferroelectric material such as lead zirconate titanate (PZT) or Ba.sub.x Sr.sub.1-x TiO.sub.3 (BST).

Abstract: A ferroelectric semiconductor random access memory (RAM) is disclosed, which comprises a memory cell array having a plurality of memory cells arranged in a matrix, each of the memory cells having an access transistor and a ferroelectric capacitor, a plurality of bit lines of open bit line structure connected with corresponding sense amplifiers, and a plurality of reference cells arranged symmetrically against the sense amplifiers for providing reference voltage to the reference input terminals of the sense amplifiers toe sense the logical states of the data stored in the memory cells. In this device, the reference voltage is provided from one of the reference cells.