Abstract: An electronic device, according to one of the various embodiments of the present disclosure, includes: a memory; a communication module that transmits and receives messages; and a processor that, when a non-IP service-based message is received, creates an IP-based message including at least some of the non-IP service-based message, and provides the created IP-based message. In addition, various embodiments are provided.

Abstract: A touch sensor includes touch electrodes in a first area and a second area, a first force sensor electrode on a same layer as the touch electrodes and spaced from a first touch electrode in the first area, a first force sensor line on a same layer as the touch electrodes and electrically connected to the first force sensor electrode, the first force sensor line being at a second side of the first touch electrode, and touch lines on a same layer as, and connected to, the touch electrodes, the touch lines including a first touch line connected to the first touch electrode and at a first side of the first touch electrode.

Abstract: In one embodiment, a method includes providing a substrate comprising a source/drain contact region and a dummy gate, forming a first etch stop layer aligned to the source/drain contact region, where the first etch stop layer does not cover the dummy gate. The method may include forming a second etch stop layer over the first etch stop layer, the second etch stop layer covering the first etch stop layer and the dummy gate. The method may include converting the dummy gate to a metal gate. The method may include removing the second etch stop layer using a plasma etching process. The method may include removing the first etch stop layer.

Abstract: Methods are provided herein for patterning extreme ultraviolet (EUV) (or lower wavelength) photoresists, such metal-oxide photoresists. A patterning layer comprising a metal-oxide photoresist is formed on one or more underlying layers provided on a substrate, and portions of the patterning layer not covered by a mask overlying the patterning layer are exposed to EUV or lower wavelengths light. A cyclic dry process is subsequently performed to remove portions of the patterning layer exposed to the EUV or lower wavelength light (i.e., the exposed portions) and develop the metal-oxide photoresist pattern. The cyclic dry process generally includes a plurality of deposition and etch steps, wherein the deposition step selectively deposits a protective layer onto unexposed portions of the patterning layer by exposing the substrate to a first plasma, and the etch step selectively etches the exposed portions of the patterning layer by exposing the substrate to a second plasma.

Abstract: A touch sensing unit, includes a plurality of first sensing electrodes and a plurality of second sensing electrodes intersecting with and insulated from the plurality of first sensing electrodes. The plurality of first sensing electrodes includes a plurality of first sensor portions and a plurality of first connection portions connecting each of the plurality of first sensor portions with one another. The plurality of second sensing electrodes includes a plurality of second sensor portions a plurality of stem sensors extended from the plurality of second sensor portions, and a plurality of second connection portions connecting each of the plurality of sensor portions with one another. Each of the plurality of first sensor portions includes a plurality of depressions indented inwardly. Each of the plurality of stem sensors is disposed such that it is at least partially surrounded by a respective depression of the plurality of depressions.

Abstract: The present disclosure relates to an integrated antenna structure. The integrated antenna structure includes a radiator and a ground plane disposed between a semiconductor substrate and the radiator. A conductive structure is separated from the ground plane by the semiconductor substrate. The conductive structure is electrically coupled to the ground plane. The semiconductor substrate has a thickness of less than approximately 100 microns.

Abstract: A voltage regulator includes an output node, a control circuit, and a power stage. The control circuit is configured to receive a power state signal from a load circuit coupled to the output node, and output a control signal based on the power state signal. The power stage includes a plurality of phase circuits coupled to the output node and is configured to enable a phase circuit of the plurality of phase circuits responsive to the control signal.

Abstract: Disclosed herein include methods of detecting and measuring enzymatic activity in coating compositions comprising one or more enzymes contained therein, for example following film formation of the coating compositions. Media-based assays and spectrophotometric-based biochemical assays for analysis of in-film enzymatic activity are provided. Methods of configuring coating compositions to enable spectrophotometric-based analysis are also provided.

Abstract: The present embodiments provide a mechanism for computing a thickness of a scanned wafer shape to determine a profile, and computing a delta correction value and a polishing end point time by using a computed PV value by the profile and a set predicted PV value and reflecting the same on the polishing time of each wafer which is under polishing. Accordingly, excellent flatness of a wafer surface can be achieved and simultaneously, a plurality of controllers can be controlled simultaneously to reduce equipment cost.

Abstract: A method (of reducing errors in a migration a first netlist to a second netlist, the first and second netlists representing corresponding first and second implementations of a circuit design under corresponding first and second semiconductor process technology (SPT) nodes, at least the second netlist being stored on a non-transitory computer-readable medium), the method including: inspecting a timing constraint list for addition candidates, the timing constraint list corresponding to an initial netlist which represents the second implementation; relative to a logic equivalence check (LEC) context, increasing a number of comparison points based on the addition candidates, resulting in first version of the second netlist; performing a LEC between the first netlist and the first version of the second netlist, thereby identifying migration errors; and revising the first version of the second netlist to reduce the migration errors, thereby resulting in a second version of the second netlist.

Abstract: An optical assembly for projecting light from a display includes a first optical waveguide, a reflective optical element configured, and a first in-coupler. The reflective optical element is configured to receive first light having first polarization from the display and to reflect the first light as second light having second polarization distinct from the first polarization. The first in-coupler is coupled with the first optical waveguide. The first in-coupler is configured to receive and transmit the first light. The first in-coupler is further configured to receive the second light and redirect a first portion of the second light so that the first portion of the second light undergoes total internal reflection inside the first optical waveguide.

Abstract: A method (of reducing errors in a migration a first netlist to a second netlist, the first and second netlists representing corresponding first and second implementations of a circuit design under corresponding first and second semiconductor process technology (SPT) nodes, at least the second netlist being stored on a non-transitory computer-readable medium), the method including: inspecting a timing constraint list for addition candidates, the timing constraint list corresponding to an initial netlist which represents the second implementation; relative to a logic equivalence check (LEC) context, increasing a number of comparison points based on the addition candidates, resulting in first version of the second netlist; performing a LEC between the first netlist and the first version of the second netlist, thereby identifying migration errors; and revising the first version of the second netlist to reduce the migration errors, thereby resulting in a second version of the second netlist.

Abstract: A touch sensor includes a base, first sensing electrode columns (FSECs), and second sensing electrode columns (SSECs). The base includes a sensing region (SR) including a rounded corner (RC), and a non-SR outside the SR. The FSECs extend in a direction on the base, each FSEC among the FSECs including first sensing electrodes (FSEs), each FSE among the FSEs including sub-electrodes. The SSECs are alternately disposed with the FSECs on the base, each SSEC among the SSECs including second sensing electrodes (SSEs). Sub-electrodes of one of adjacent FSEs among the FSEs are electrically connected to respective sub-electrodes of another of the adjacent FSEs. A sub-electrode closest to the RC among the sub-electrodes includes a rounded edge (RE) corresponding to the RC. A SSE closest to the RC among the SSEs includes a RE corresponding to the RC, and a protrusion part protruding toward the sub-electrode including the RE.

Abstract: The present invention provides a detection device and a method with simplified computing manner A transmitter transmits detection signals to an environment to detect a target. At least a portion of the detection signals are reflected by the target to generate a plurality of reflection signals. A receiver comprises a plurality of receiving units. Each of the receiving units receives the reflection signals to generate a receiving signal. A processing module connected to the receiver includes a conversion unit, an integration unit and a computing unit. The conversion unit converts the receiving signals into transformation signals by a time-domain to frequency-domain transformation. The integration unit integrates the transformation signals into a first integration signal and a second integration signal. The computing unit decomposes the first integration signal and the second integration signal to 1D arrays.

Abstract: A clock distribution circuit configured to output a clock signal includes a first circuit configured to use a reference clock signal to provide first and second reference signals, wherein the second reference signal indicates whether the first reference signal is locked with the reference clock signal; a second circuit configured to use the reference clock signal to provide an output signal and an indication signal indicative whether the output signal is locked with the reference clock signal; and a monitor circuit, coupled to the first and second circuits, and configured to use at least one of the first reference signal, the second reference signal, the output signal, and the indication signal to determine whether the second circuit is functioning correctly.

Abstract: Electronic design automation (EDA) of the present disclosure, in various embodiments, optimizes designing, simulating, analyzing, and verifying of one or more electronic architectural designs for an electronic device. The EDA of the present disclosure identifies one or more electronic architectural features from the one or more electronic architectural designs. In some situations, the EDA of the present disclosure can manipulate one or more electronic architectural models over multiple iterations using a machine learning process until one or more electronic architectural models from among the one or more electronic architectural models satisfy one or more electronic design targets. The EDA of the present disclosure substitutes the one or more electronic architectural models that satisfy the one or more electronic design targets for the one or more electronic architectural features in the one or more electronic architectural designs to optimize the one or more electronic architectural designs.

Abstract: A device is disclosed. The cell block includes a pin disposed at a Nth metal layer in a cell layout. The first metal interconnect is disposed at a (N+1)th metal layer above the Nth metal layer and stacked over the pin, and electrically coupled to the pin. The second interconnects are disposed at a (N+2)th metal layer and stacked over the first metal interconnect, and parallel to each other. The second metal interconnects are electrically coupled to the first metal interconnect, and forming an equivalent tapping point of the pin of the cell block. The equivalent tapping point and the pin are vertically overlapped with each other, and fabrication of the device is initiated after a DRC or a SEM simulation test is passed. A first via connects the first metal interconnect to the pin, and the at least one first metal interconnect is perpendicular to the pin.

Abstract: Aspects of the invention include selective video-watching by analyzing user behavior and video content. A non-limiting example computer-implemented method includes playing, by a processor, a target video with a pre-fetched frame. The method extracts, by the processor, a feature from the pre-fetched frame and stores, by the processor, the feature in a repository. The method provides, by the processor, a plurality of actions to a target user based on the feature stored in the repository. The method receives, by the processor, one of the plurality of actions from the target user; and performs, by the processor, the one of the plurality of actions received from the target user.

Abstract: A transformer includes a magnetic core, a first coil unit and a second coil unit. The first coil unit is disposed within the magnetic core and includes a laminated board having layers laminated therein and conductive patterns. Respective ones of the conductive patterns are disposed on the laminated layers. The second coil unit includes a conductive wire spaced apart from the conductive patterns of the laminated board by an insulating distance. The conductive wire includes a triple-insulated wire surrounded by three sheets of insulating paper to maintain the insulating distance from the conductive patterns.

Abstract: The present invention relates to a method for producing a 3- to 3.5-valent vanadium solution from a 4-valent vanadium solution by a catalytic reaction in the presence of a reducing agent, which generates a gas product during oxidation; a method for producing an electrolyte for a vanadium redox flow battery; and an apparatus for producing a liquid electrolyte for a vanadium redox flow battery. The present invention is characterized in that when a 3- to 3.5-valent vanadium electrolyte is produced from a 4-valent vanadium electrolyte by a catalytic reaction in the presence of a reducing agent, which generates a gas product during oxidation, the gas product produced in the catalytic reaction is captured with inert gas bubbles, which are carrier gases, and is removed from the reaction solution of the catalytic reaction by gas-liquid phase separation, thereby accelerating the catalytic reaction towards the forward reaction.