Patents by Inventor Yun Liang

Yun Liang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20250148750
    Abstract: Methods, apparatus, and computer program products for multimodal artificial intelligence-based communication systems are provided herein. A computer-implemented method includes generating, using a first set of one or more artificial intelligence techniques, identifying information for one or more objects detected in image data associated with at least one user query; generating at least one updated version of the at least one user query by processing, using a second set of one or more artificial intelligence techniques, at least a portion of the at least one user query in conjunction with at least a portion of the identifying information for the one or more objects; generating at least one response to the at least one updated version of the at least one user query; and performing one or more automated actions based at least in part on the at least one response.
    Type: Application
    Filed: November 8, 2023
    Publication date: May 8, 2025
    Inventors: Yuan Yuan Ding, Yang Liu, Jing Zhang, Yu Pan, Shi Yun Liang
  • Patent number: 12292819
    Abstract: Embodiments of the invention are directed to computer-implemented methods of analyzing a web-based software application. A non-limiting example of the computer implemented method includes generating, using a processor system, a set of to-be-tested element-event pairs of the web-based software application. A set of compatibility tests is received at the processor system, where the set of compatibility tests is operable to perform compatibility testing of a corresponding set of element-event pairs. A comparison is performed between the set of to-be-tested element-event pairs and the corresponding set of element-event pairs. A compatibility testing recommendation is generated based at least in part on a result of the comparison.
    Type: Grant
    Filed: September 21, 2022
    Date of Patent: May 6, 2025
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Hong Liang Zhao, Qi Li, Yan Hui Wang, Jia Lei Rui, Qun Wei, Yun Juan Yang
  • Publication number: 20250140277
    Abstract: Method, system, device, and non-transitory computer-readable medium for joining a virtual participant in a conversation. In some examples, a computer-implemented method includes: identifying a first conversation scheduled to be participated by a first group of actual participants; joining a first virtual participant into the first conversation; obtaining, via the first virtual participant, a first set of audio data associated with the first conversation while the first conversation occurs; transcribing, via the first virtual participant, the first set of audio data into a first set of text data while the first conversation occurs; and presenting the first set of text data to the first group of actual participants while the first conversation occurs.
    Type: Application
    Filed: January 6, 2025
    Publication date: May 1, 2025
    Inventors: AMRO YOUNES, WINFRED JAMES, TAO XING, CHENG YUAN, YUN FU, SIMON LAU, ROBERT FIREBAUGH, SAM LIANG
  • Publication number: 20250142951
    Abstract: Embodiments of present disclosure relates to forming isolation structures in gate structures to prevent current leakage through source/drain regions (EPI), transistors, and silicon substrate. The isolation structures are arranged in a pattern with a long isolation structure adjacent a short isolation structure. The isolation structures may be formed in the gate structure prior to or after the replacement gate sequence.
    Type: Application
    Filed: March 12, 2024
    Publication date: May 1, 2025
    Inventors: Tzu-Ging LIN, Hung-Yu LIN, Chia-Chin LEE, Chun-Liang LAI, Yun-Chen WU
  • Publication number: 20250138837
    Abstract: Mechanisms are provided, in a data processing system specifically configured to implement a computer container management platform in which Operators and Operator Controllers are used to manage at least one custom resource associated with a containerized application, to receive an Operator Deployment comprising an Operator Container having an Operator with a plurality of Operator Controllers. A process control manager (PCM) process configures each Operator Controller to execute as a separate process from each of the other Operator Controllers of the Operator Container. The Operator of the Operator Container is run at least by executing the Operator Controllers of the Operator in separate Operator runtimes based on the configuring of the Operator Controllers.
    Type: Application
    Filed: October 27, 2023
    Publication date: May 1, 2025
    Inventors: Zhi Li Guan, Hai Wei F Fang, Guo Liang Huang, Shi Su, Fang Tai L Li, Yun Diao
  • Publication number: 20250143046
    Abstract: A light emitting diode package structure includes one or more lead frame units, a light emitting element, and an encapsulation unit that completely covers the light emitting element and partially covers the lead frame units. Each lead frame unit includes a chip-mounted portion, a first electrode portion, and a second electrode portion. The first and the second electrode portion extend along a first direction, and are disposed on two sides of the chip-mounted portion. Each lead frame unit further includes multiple first connecting portions extending from the chip-mounted portion along the first direction, and multiple second connecting portions formed by extension of the first and the second electrode portion along a second direction. The light emitting element is fixed to the chip-mounted portion and electrically connected to the electrode portions. A lead frame that includes the at least one lead frame unit is also provided.
    Type: Application
    Filed: October 25, 2024
    Publication date: May 1, 2025
    Inventors: HSIN-HUI LIANG, CHENG-HONG SU, CHEN-HSIU LIN, CHIH-LI YU, CHENG-HAN WANG, SHENG-YUN WANG
  • Publication number: 20250122202
    Abstract: Disclosed are a compound of formula I or a pharmaceutically acceptable salt thereof, and use thereof in regulating and controlling an EGFR tyrosine kinase activity or preventing and treating an EGFR-related disease. The EGFR inhibitor of formula I has an inhibitory activity on EGFR D770-N771 ins NPG and NPG/T790M kinases, and an inhibitory effect on an EGFR-Del19/T790M/C797S kinase and cell proliferation of a KC-0122:Ba/F3EGFR-L858R/T790M/C797S three-mutation cell line and a KC-0116:Ba/F3EGFR-Del19/T790M/C797S three-mutation cell line.
    Type: Application
    Filed: September 16, 2022
    Publication date: April 17, 2025
    Inventors: Guimin Zhang, Hao Zhang, Jingchun Yao, Jiang Yuan, Guifang Zhao, Rui Li, Guangyan Li, Yun Zhao, Hongbao Liang, Zhenjun Zhang, Xiangxia Zhu
  • Publication number: 20250126841
    Abstract: A structure includes a plurality of semiconductor regions, a first gate stack and a second gate stack immediately neighboring each other, a first fin isolation region in the first gate stack, and a second fin isolation region in the second gate stack. The first fin isolation region and the second fin isolation region have a sideway overlap having an overlap distance being equal to or greater than a pitch of the plurality of semiconductor regions. The overlap distance is measured in a direction parallel to lengthwise directions of the first gate stack and the second gate stack. A plurality of source/drain regions are on opposing sides of the first gate stack and the second gate stack to form a plurality of transistors.
    Type: Application
    Filed: February 29, 2024
    Publication date: April 17, 2025
    Inventors: Tzu-Ging Lin, Chun-Liang Lai, Yun-Chen Wu
  • Publication number: 20250126870
    Abstract: A semiconductor device structure and methods of forming the same are described. The structure includes a gate dielectric layer disposed over a substrate, a gate electrode layer disposed over the gate dielectric layer, and a first gate spacer disposed adjacent the gate dielectric layer. The first gate spacer includes an inner surface facing the gate dielectric layer and an outer surface opposite the inner surface, and the first gate spacer includes a fluorine concentration that decreases from the inner surface and the outer surface towards a center of the first gate spacer. The structure further includes a second gate spacer disposed on the outer surface of the first gate spacer, and the second gate spacer includes a fluorine concentration that decreases from an outer surface towards an inner surface.
    Type: Application
    Filed: October 15, 2023
    Publication date: April 17, 2025
    Inventors: Zheng-Yong LIANG, Wei-Ting YEH, Fu-Ting YEN, Hung-Yu YEN, Chien-Hung LIN, Kuei-Lin CHAN, Yu-Yun PENG, Keng-Chu LIN
  • Publication number: 20250107170
    Abstract: Methods for isolating two adjacent transistors are disclosed. A substrate has a first semiconducting fin on a first region and a second semiconducting fin on a second region, and the first semiconducting fin and the second semiconducting fin contact each other at a jog region. A dummy gate within or adjacent the jog region is removed to expose a portion of the first semiconducting fin and form an isolation volume. Etching is performed to remove the exposed portion of the first semiconducting fin and create a trench in the substrate. The trench and the isolation volume are filled with at least one dielectric material to form an electrically isolating structure between the first region and the second region. Additional dummy gates in each region can be removed and replaced with an electrically conductive material to form two adjacent transistors electrically isolated from each other.
    Type: Application
    Filed: September 25, 2023
    Publication date: March 27, 2025
    Inventors: Yun-Chen WU, Tzu-Ging LIN, Jih-Jse LIN, Jun-Ye LIU, Chun-Liang LAI, Chih-Yu HSU
  • Publication number: 20250081493
    Abstract: A continuous metal on diffusion edge (CMODE) may be used to form a CMODE structure in a semiconductor device after a replacement gate process that is performed to replace the polysilicon dummy gate structures of the semiconductor device with metal gate structures. The CMODE process described herein includes removing a portion of a metal gate structure (as opposed to removing a portion of a polysilicon dummy gate structure) to enable formation of the CMODE structure in a recess left behind by removal of the portion of the metal gate structure.
    Type: Application
    Filed: September 5, 2023
    Publication date: March 6, 2025
    Inventors: Tzu-Ging LIN, Chen-Yu TAI, Chun-Liang LAI, Yun-Chen WU, Shun-Hui YANG
  • Patent number: 12240006
    Abstract: An all-plastic pump comprising an outer cover, a plastic spring, an inner cover and a pressing head. The pump includes an accessory cavity in the outer cover, with a conveying hole. A tubular plastic spring is positioned within the cavity, surrounding the conveying hole. Supporting rods are arranged circumferentially on an inner wall of the plastic spring's port, with one end of the rods connected to a baffle. The inner cover surrounds the plastic spring, and a stop tube is inserted through the supporting rods, with its port sealing against the baffle. The pressing head, mounted in a pressable manner, includes a discharging hole, pressing sheet, and conveying tube. When pressed, the pressing sheet compresses the plastic spring, causing separation between the baffle and stop tube, allowing fluid discharge.
    Type: Grant
    Filed: September 8, 2020
    Date of Patent: March 4, 2025
    Assignee: Guangzhou Shanggong Plastic Co., Ltd
    Inventors: Qiquan Liang, Yun Huang, Haoyu Liang
  • Publication number: 20250062138
    Abstract: A method for fabricating a package structure is provided. The method includes premixing cellulose nanofibrils (CNFs) and a graphene material in a solvent to form a solution; removing the solvent from the solution to form a composite filler; mixing a prepolymeric material with the composite filler to form a composite material; and performing a molding process using the composite material.
    Type: Application
    Filed: August 18, 2023
    Publication date: February 20, 2025
    Applicants: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD., NATIONAL TAIWAN UNIVERSITY
    Inventors: Tzu-Hsuan CHANG, Rong-Teng Lin, Bi-Xian Wu, Teng-Chin Hsu, Yun-Hong Yang, Chien-Liang Chen, Jam-Wem Lee, Kuo-Ji Chen, Wun-Jie Lin
  • Publication number: 20250043217
    Abstract: A stripper composition and a method for stripping a photoresist are provided. The stripper composition includes an ether-alcohol-based organic solvent (A), another organic solvent (B), an alkaline substance (C), a substrate corrosion inhibitor (D), and water (E). The another organic solvent (B) does not include the ether-alcohol-based organic solvent. The alkaline substance (C) includes an organic base (C1), an inorganic base (C2), or a combination thereof. Based on a total usage amount of 100 parts by weight of the stripper composition, a usage amount of the ether-alcohol-based organic solvent (A) is 7 parts by weight to 70 parts by weight, and a usage amount of the substrate corrosion inhibitor (D) is greater than 0 part by weight and less than 18 parts by weight.
    Type: Application
    Filed: July 21, 2024
    Publication date: February 6, 2025
    Applicant: Advanced Echem Materials Company Limited
    Inventors: Chi-Liang He, Yun-Ju Chiang, Ting-Ruei Xu, Ming-Chia Tsai
  • Patent number: 12218051
    Abstract: Exemplary embodiments for redistribution layers of integrated circuit components are disclosed. The redistribution layers of integrated circuit components of the present disclosure include one or more arrays of conductive contacts that are configured and arranged to allow a bonding wave to displace air between the redistribution layers during bonding. This configuration and arrangement of the one or more arrays minimize discontinuities, such as pockets of air to provide an example, between the redistribution layers during the bonding.
    Type: Grant
    Filed: July 20, 2022
    Date of Patent: February 4, 2025
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Cheng-Yuan Li, Kuo-Cheng Lee, Yun-Wei Cheng, Yen-Liang Lin
  • Publication number: 20250032621
    Abstract: A drug conjugate includes a structure shown by the following formula: Z-(linker-[R]m)n. In the formula, Z is a drug compound, R is a sugar, and m and n are independently an integer from 1 to 6. The drug compound Z is a hepatitis virus targeting drug, a hepatitis B virus (HBV) drug, an inhibitor of apoptosis protein (IAP) antagonist, a multidrug resistance (MDR) inhibitor, or analogues, precursors, prodrugs, derivatives thereof.
    Type: Application
    Filed: May 30, 2024
    Publication date: January 30, 2025
    Applicant: SeeCure Taiwan Co., Ltd.
    Inventors: Wuu-Jyh Lin, Min-Ching Chung, Chi-Shiang Ke, Ya-Chen Tseng, Chin-Yu Liang, Yen-Chun Lee, Hsin-Jou Li, Tai-Yun Huang, Nai-Chen Hsueh, Yan-Feng Jiang
  • Publication number: 20250022715
    Abstract: Methods for fabricating semiconductor devices are provided. An exemplary method includes forming fins in a dense region and in an isolated region of a semiconductor substrate; performing a plasma dry etch process to remove a portion of at least one selected fin to form a first trench in the dense region and to remove a portion of at least one selected fin in the isolated region to form a second trench in the isolated region, wherein the plasma dry etch process includes: performing a passivation-oriented process and an etchant-oriented process; and controlling the passivation-oriented process and the etchant-oriented process to form the first trench with a desired first critical dimension and first depth and to form the second trench with a desired second critical dimension and second depth.
    Type: Application
    Filed: July 10, 2023
    Publication date: January 16, 2025
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Tzu-Ging Lin, Ya-Yi Tsai, Chun-Liang Lai, Yun-Chen WU, Shu-Yuan Ku
  • Patent number: 12045310
    Abstract: Disclosed is a method and system for achieving optimal separable convolutions, the method is applied to image analyzing and processing and comprises steps of: inputting an image to be analyzed and processed; calculating three sets of parameters of a separable convolution: an internal number of groups, a channel size and a kernel size of each separated convolution, and achieving optimal separable convolution process; and performing deep neural network image process. The method and system in the present disclosure adopts implementation of separable convolution which efficiently reduces a computational complexity of deep neural network process. Comparing to the FFT and low rank approximation approaches, the method and system disclosed in the present disclosure is efficient for both small and large kernel sizes and shall not require a pre-trained model to operate on and can be deployed to applications where resources are highly constrained.
    Type: Grant
    Filed: September 8, 2021
    Date of Patent: July 23, 2024
    Assignee: Peng Cheng Laboratory
    Inventors: Tao Wei, Yonghong Tian, Yaowei Wang, Yun Liang, Chang Wen Chen, Wen Gao
  • Publication number: 20230264553
    Abstract: A cooling structure for a drive system, includes a motor assembly. The motor assembly includes a rotary shaft and a cooling tube having an inner hole. The rotary shaft includes a mounting hole for receiving the cooling tube. An annular water channel is formed between an outer wall of the cooling tube and an inner wall of the mounting hole. The inner hole and the annular water channel form a rotor cooling water channel.
    Type: Application
    Filed: April 28, 2023
    Publication date: August 24, 2023
    Inventors: Heping LING, Zhen ZHAI, Linna LIU, Yun LIANG, Yuchao XIONG
  • Publication number: 20230075664
    Abstract: Disclosed is a method and system for achieving optimal separable convolutions, the method is applied to image analyzing and processing and comprises steps of: inputting an image to be analyzed and processed; calculating three sets of parameters of a separable convolution: an internal number of groups, a channel size and a kernel size of each separated convolution, and achieving optimal separable convolution process; and performing deep neural network image process. The method and system in the present disclosure adopts implementation of separable convolution which efficiently reduces a computational complexity of deep neural network process. Comparing to the FFT and low rank approximation approaches, the method and system disclosed in the present disclosure is efficient for both small and large kernel sizes and shall not require a pre-trained model to operate on and can be deployed to applications where resources are highly constrained.
    Type: Application
    Filed: September 8, 2021
    Publication date: March 9, 2023
    Inventors: Tao WEI, Yonghong TIAN, Yaowei WANG, Yun LIANG, Chang Wen CHEN, Wen GAO