Patents by Inventor Yun Liang

Yun Liang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20050169013
    Abstract: A backlight module and a liquid crystal display utilizing the same. The backlight module has a heat-dissipating port and a thermally actuated device disposed therein. When the temperature inside the backlight module exceeds a predetermined limit, the thermally actuated device starts to open the heat-dissipating port. When the temperature inside the backlight module drops below the predetermined limit, the thermally actuated device closes the heat-dissipating port. The extent of the port controlled by the thermally actuated device varies with the temperature inside the backlight module.
    Type: Application
    Filed: April 26, 2004
    Publication date: August 4, 2005
    Inventors: Chuan-Pei Yu, Yun-Liang Huang, Hsin-Kuo Chang, Hsin-Jou Chiu
  • Patent number: 6872662
    Abstract: A method for detecting the endpoint of a chemical mechanical polishing (CMP) process uses the slope variation of temperature difference of polishing pad. The method combines temperature measurement at polishing pad and atmosphere, and numerical analysis to figure out the curve of temperature difference variation versus polishing time. The endpoint of CMP is determined by the change of the slope of the curve. The method allows endpoint to be detected in-situ at the polishing apparatus, without stopping polishing process.
    Type: Grant
    Filed: October 27, 2003
    Date of Patent: March 29, 2005
    Inventors: Hong Hocheng, Yun-Liang Huang
  • Publication number: 20050037616
    Abstract: A method of improving surface planarity of a wafer. The method includes forming a first thin-film layer on the wafer using CVD in a first thin film deposition apparatus having at least one gas injector, relative to which the wafer has a first orientation, and forming a second thin-film layer on the wafer using CVD. The second deposition takes place in a second thin film deposition apparatus having at least one second gas injector arranged the same as that in the first thin film deposition apparatus, the wafer having a second orientation relative to the gas injector in the second thin film deposition apparatus. A first angle between the two orientations results in the second apparatus' injector distributing material in a different area from that of the first gas injector.
    Type: Application
    Filed: August 11, 2003
    Publication date: February 17, 2005
    Inventors: Chien-Ching Chan, Yun-Liang Ouyang, Yung-Wei Lu
  • Patent number: 6749305
    Abstract: An optical module is composed of three light-guide units and a holder for the units. Each of the light-guide units is made of a mirror plane used for reflecting and transmitting light installed between two prisms via the use of circularly applied glue. The holder includes three installation areas one installation area for each light-guide unit. Additionally, the holder has two frames that are arranged perpendicularly to each other and each frame is installed perpendicularly to the joining sides of two installation areas i.e. one frame is installed perpendicular to the side where installation area 1 and installation area 2 meet and the other frame is installed perpendicular to the side where installation area 2 and installation area 3 meet.
    Type: Grant
    Filed: August 29, 2003
    Date of Patent: June 15, 2004
    Assignee: Primax Display Corpration
    Inventors: Chung-Feng Tsao, Bun-Liou Liau, Kao-Chun Huang, Yun-Liang Chu
  • Publication number: 20030010712
    Abstract: The present invention relates to a process for biochemical treatment of waste water. The process uses a nano material such as carbon black to induce micro to degrade organic pollutants in the waste water which are generally unable or hard to be degraded and thereby greatly enhance the effect of biological cleaning of waste water. The effect is more prominent for the waste water that is hard to treat by the conventional biochemical treatment, high concentration waste water, and highly poisonous waste water. The process of the present invention is widely usable in the aerobic, oxygen-facultative or anaerobic biochemical treatment systems.
    Type: Application
    Filed: April 18, 2002
    Publication date: January 16, 2003
    Inventors: Minghua Gao, Jincheng Xue, Pu Zhao, Jingjing Ye, Yun Liang, Xiuhua Hou, Linlin Gao, Lingxu Liu, Benzhong Chai
  • Publication number: 20020168848
    Abstract: The present invention provides a method of fabricating an interconnect structure. First, a semiconductor substrate comprising a conductive region containing a metal line and a hole is provided. Next, a titanium layer is formed on the semiconductor substrate. Next, a first titanium nitride layer is formed on the titanium layer by chemical vapor deposition. Finally, a second titanium nitride layer is formed on the first titanium nitride layer by physical vapor deposition.
    Type: Application
    Filed: August 21, 2001
    Publication date: November 14, 2002
    Inventors: Yun-Liang Ouyang, Chao-Yuan Huang
  • Publication number: 20020109974
    Abstract: A primary circuit board is provided with an opening. A component is mounted on a secondary circuit board. The secondary circuit board is then mounted over the opening of the primary circuit board with the component disposed within the opening. An exposure height of the component over the primary circuit board is thus reduced, the exposure height being measured from a top surface of the component to a top surface of the primary circuit board.
    Type: Application
    Filed: February 9, 2001
    Publication date: August 15, 2002
    Inventors: Fang-Yu Chu, Yi-Lung Chen, Pao-Hsin Chiang, Meng-Yu Jiang, Yun-Liang Chu
  • Publication number: 20020055202
    Abstract: The invention provides a method for forming a dielectric layer in a semiconductor device by using etch stop layers, and a semiconductor structure formed by the method. The method in accordance with the invention comprises: providing a semiconductor substrate having raised portions and recessed portions; forming a first etch stop layer covering the raised portions and the recessed portions; forming a dielectric layer covering an upper surface of the first etch stop layer, wherein the dielectric layer has a thickness substantially smaller than that of each of the raised portions; forming a second etch stop layer covering the dielectric layer; and performing a planarizing step for polishing the second etch stop layer and the dielectric layer until exposing the first etch stop layer on an upper surface of the raised portions, and remaining a plurality of remaining portions of the second etch stop layer on the planarized surface, and remaining the dielectric layer between raised portions.
    Type: Application
    Filed: August 15, 2001
    Publication date: May 9, 2002
    Inventors: Chih-Sheng Yang, Kuei-Chang Tsai, Chih-Hung Shu, Yun-Liang Ouyang
  • Patent number: 6384482
    Abstract: The invention provides a method for forming a dielectric layer in a semiconductor device by using etch stop layers, and a semiconductor structure formed by the method. The method in accordance with the invention comprises: providing a semiconductor substrate having raised portions and recessed portions; forming a first etch stop layer covering the raised portions and the recessed portions; forming a dielectric layer covering an upper surface of the first etch stop layer, wherein the dielectric layer has a thickness substantially smaller than that of each of the raised portions; forming a second etch stop layer covering the dielectric layer; and performing a planarizing step for polishing the second etch stop layer and the dielectric layer until exposing the first etch stop layer on an upper surface of the raised portions, and remaining a plurality of remaining portions of the second etch stop layer on the planarized surface, and remaining the dielectric layer between raised portions.
    Type: Grant
    Filed: August 15, 2001
    Date of Patent: May 7, 2002
    Assignee: Mosel Vitelic Inc.
    Inventors: Chih-Sheng Yang, Kuei-chang Tsai, Chih-hung Shu, Yun-liang Ouyang
  • Patent number: 6336787
    Abstract: A wafer transfer method using a robot arm for sucking the front-side of the uppermost one of a plurality of wafers stored in a cassette, and for transferring the wafer having a tape adhered to the front-side thereof to a semiconductor tape-peeling device for tape-peeling. Although the wafer warps, the undesired effect that the robot arm crashes any of the wafers can be avoided by using this method.
    Type: Grant
    Filed: April 17, 2000
    Date of Patent: January 8, 2002
    Assignee: Mosel Vitelic, Inc.
    Inventors: Chin-hsiang Chang, Yun-liang Ouyang, Chih-shen Yang, Kuei-chang Tsai
  • Patent number: 6117780
    Abstract: The present invention discloses a chemical mechanical polishing method with in-line thickness detection. First, the semiconductor wafer is loaded into CMP equipment and is putted on a loading table for the preparation of a CMP process. The CMP process is performed on the wafer for polishing. The CMP process is interrupted and the thickness of a polished thin film layer is detected by using an in-line thickness measurement technique. The thickness is determined whether or not being accepted by a specification of the CMP process. As the thickness is accepted by the specification, the wafer is cleaned, dried and moved out from the CMP equipment. Alternatively, the thickness is not accepted by the specification, it must be determined whether or not the thickness is less than the low limit of the specification. As the thickness is smaller than the low limit, the wafer is cleaned, dried after it is moved out from the CMP equipment.
    Type: Grant
    Filed: April 22, 1999
    Date of Patent: September 12, 2000
    Assignee: Mosel Vitelic Inc.
    Inventors: Kuei-Chang Tsai, Chin-Hsiang Chang, Li-Chun Hsien, Yun-Liang Ouyang