Abstract: The present disclosure describes a method of forming low thermal budget dielectrics in semiconductor devices. The method includes forming, on a substrate, first and second fin structures with an opening in between, filling the opening with a flowable isolation material, treating the flowable isolation material with a plasma, and removing a portion of the plasma-treated flowable isolation material between the first and second fin structures.

Abstract: An integrated circuit structure in which a gate overlies channel region in an active area of a first transistor. The first transistor includes a channel region, a source region and a drain region. A conductive contact is coupled to the drain region of the first transistor. A second transistor that includes a channel region, a source region a drain region is adjacent to the first transistor. The gate of the second transistor is spaced from the gate of the first transistor. A conductive via passes through an insulation layer to electrically connect to the gate of the second transistor. An expanded conductive via overlays both the conductive contact and the conductive via to electrically connect the drain of the first transistor to the gate of the second transistor.

Abstract: A manufacturing method of an electronic element module is provided. The method includes: disposing a plurality of first micro-light-emitting diodes on a first temporary substrate; and replacing at least one defective micro-light-emitting diode of the first micro-light-emitting diodes with at least one second micro-light-emitting diode. The first micro-light-emitting diodes and at least one second micro-light-emitting diode are distributed on the first temporary substrate. The first micro-light-emitting diodes and at least one second micro-light-emitting diode have same properties, and at least one of the appearance difference, the height difference and the orientation difference exists between the first micro-light-emitting diodes and at least one second micro-light-emitting diode. A semiconductor structure and a display panel are also provided.

Abstract: The present invention discloses a force feedback hand training method including: providing a training game content and adjusting the training game content based on predetermined parameters; displaying the training game content on a display; determining whether an input button position of at least one input signal from a hand training device matches a predetermined input button position; and storing a determination result in a storage module.

Abstract: A method for removing a heavy metal from water includes subjecting a microbial solution containing a liquid culture of a urease-producing bacterial strain and a reaction solution containing a manganese compound and urea to a microbial-induced precipitation reaction, so as to obtain biomineralized manganese carbonate (MnCO3) particles, admixing the biomineralized MnCO3 particles with water containing a heavy metal, so that the biomineralized MnCO3 particles adsorb the heavy metal in the water to form a precipitate, and removing the precipitate from the water.

Abstract: An embodiment is a semiconductor structure. The semiconductor structure includes a fin on a substrate. A gate structure is over the fin. A source/drain is in the fin proximate the gate structure. The source/drain includes a bottom layer, a supportive layer over the bottom layer, and a top layer over the supportive layer. The supportive layer has a different property than the bottom layer and the top layer, such as a different material, a different natural lattice constant, a different dopant concentration, and/or a different alloy percent content.

Abstract: Embodiments of this application relate to the video coding and compression field, and disclose an encoding method and apparatus, and a decoding method and apparatus, to resolve a problem that an existing split mode cannot satisfy a relatively complex texture requirement. The decoding method specifically includes: parsing a bitstream to determine a basic split mode for a current to-be-decoded picture block and a target derivation mode for a subpicture block of the current to-be-decoded picture block; splitting the current to-be-decoded picture block into N subpicture blocks in the basic split mode, where N is an integer greater than or equal to 2; deriving one derived picture block from at least two adjacent subpicture blocks in the N subpicture blocks in the target derivation mode; and decoding the derived picture block.

Abstract: A device includes a first dielectric layer, a first conductor, an etch stop layer, a second dielectric layer, and a second conductor. The first conductor is in the first dielectric layer. The etch stop layer is over the first dielectric layer. The etch stop layer has a first surface facing the first dielectric layer and a second surface facing away from the first dielectric layer, and a concentration of carbon in the etch stop layer periodically varies from the first surface to the second surface. The second dielectric layer is over the etch stop layer. The second conductor is in the second dielectric layer and the etch stop layer and electrically connected to the first conductor.

Abstract: A fluid control assembly and a fluid control device are provided. The fluid control assembly includes a valve body component and a valve core component. At least part of the valve core component is located in a valve cavity. The valve body component is provided with a body portion and a protruding portion. The body portion forms at least part of a wall portion of the valve cavity, and the protruding portion protrudes from the peripheral wall of the body portion. The fluid control assembly is provided with a first flow channel, and at least part of the first flow channel is located in the valve core component. The protruding portion is provided with two or more lugs, at least some of the lugs are provided with the second flow channels, and circulation ports of at least some of the second flow channels have the same orientation.

Abstract: A drive device includes a housing, a motor and a transmission assembly; the housing includes a first casing and a second casing; the first casing includes a first protruding portion and a second protruding portion; the second casing includes a third protruding portion; the transmission assembly includes a first-stage worm, a second-stage worm and a transmission wheel; the first-stage worm includes a first tooth-shaped portion; the second-stage worm includes a second tooth-shaped portion; the first protruding portion and the second protruding portion both limitedly cooperate with the second-stage worm; along the axial direction of the second tooth-shaped portion, the first protruding portion is located on one side of the second tooth-shaped portion; the second protruding portion is located on the other side of the second tooth-shaped portion; and the distance between the third protruding portion and the transmission wheel is within a preset range.

Abstract: A method for generating analog schematic diagram based on building block classification and reinforcement learning is disclosed. First of all, deeper relationship features among devices with building block classification are obtained. Secondly, the device leveling gives an initial device placement topology resulting from the current/signal flows in the circuit netlist. Thirdly, reinforcement learning is applied to refine placement and routing topologies by embedding the building blocks and current/signal flow information into feature vectors. Pattern routing and maze routing algorithms are performed for local and global interconnections, respectively, followed by placement adjustment for density balancing and space minimization to obtain aesthetic analog circuit schematics.

Abstract: A memory array and an operation method of the memory array are provided. The memory array includes first and second ferroelectric memory devices formed along a gate electrode, a channel layer and a ferroelectric layer between the gate electrode and the channel layer. The ferroelectric memory devices include: a common source/drain electrode and two respective source/drain electrodes, separately in contact with a side of the channel layer opposite to the ferroelectric layer, wherein the common source/drain electrode is disposed between the respective source/drain electrodes; and first and second auxiliary gates, capacitively coupled to the channel layer, wherein the first auxiliary gate is located between the common source/drain electrode and one of the respective source/drain electrodes, and the second auxiliary gate is located between the common source/drain electrode and the other respective source/drain electrode.

Abstract: A semiconductor arrangement includes a first dielectric feature passing through a semiconductive layer and a first dielectric layer over a substrate. The semiconductor arrangement includes a conductive feature passing through the semiconductive layer and the first dielectric layer and electrically coupled to the substrate. The conductive feature is adjacent the first dielectric feature and electrically isolated from the semiconductive layer by the first dielectric feature.

Abstract: An electronic device protecting casing with heating function includes: a casing; a battery box within the casing; an interior of the battery box being arranged with a battery, a back side of the battery box being formed with an opening for receiving the battery; an outer cover serving to seal the opening; an inner side of the outer cover being formed with a heat isolation sheet; a heating unit being installed within the casing for heating the tablet computer; the heating unit including an electric heating plate. When power of the battery is transferred to the electric heating plate, the electric heating plate generates heat power and then transfers the power to the tablet computer for heating it; and a control circuit is installed within the casing; the electric heating plate is connected to the battery through a control switch; and the control circuit is connected to the control switch.

Abstract: A detection system and method for the migrating cell is provided. The system is configured to detect a migrating cell combined with an immunomagnetic bead. The system includes a platform, a microchannel, a magnetic field source, a coherent light source and an optical sensing module. The microchannel is configured to allow the migrating cell to flow in it along a flow direction. The magnetic field source is configured to provide magnetic force to the migrating cell combined with the immunomagnetic bead. The magnetic force includes at least one magnetic force component and the magnetic force component is opposite to the flow direction of the microchannel. The coherent light source is configured to provide the microchannel with the coherent light. The optical sensing module is configured to receive the interference light caused by the coherent light being reflected by the sample inside the microchannel.

Abstract: Applications of butylidenephthalide (BP), comprising the use of BP in providing a kit for promoting differentiation of stem cells into brown adipose cells, and the use of BP in preparing a medicament, wherein the medicament is used for inhibiting the accumulation of white adipose cells, promoting the conversion of white adipose cells into brown adipose cells, inhibiting weight gain and/or reducing the content of triglycerides, glucose, and total cholesterol in blood.

Abstract: The invention relates to compounds of formula (I) with low cytotoxicity for blocking the ubiquitination-proteasome system in diseases. Accordingly, these compounds can be used in treatment of disorders including, but not limited to, cancers.

Abstract: A micro light emitting diode structure including an epitaxial structure, a first insulating layer and a second insulating layer is provided. The epitaxial structure includes a first type semiconductor layer, a light emitting layer and a second type semiconductor layer. The first type semiconductor layer, the light emitting layer and a first portion of the second type semiconductor layer form a mesa. A second portion of the second type semiconductor layer is recessed relative the mesa to form a mesa surface. The first insulating layer covers from a top surface of the mesa to the mesa surface along a first side surface of the mesa, and exposes the second side surface. The second insulating layer directly covers a second side surface of the second portion, wherein a thickness ratio of the first insulating layer to the second insulating layer is between 10 and 50.

Abstract: A device includes: a complementary transistor including: a first transistor having a first source/drain region and a second source/drain region; and a second transistor stacked on the first transistor, and having a third source/drain region and a fourth source/drain region, the third source/drain region overlapping the first source/drain region, the fourth source/drain region overlapping the second source/drain region. The device further includes: a first source/drain contact electrically coupled to the third source/drain region; a second source/drain contact electrically coupled to the second source/drain region; a gate isolation structure adjacent the first and second transistors; and an interconnect structure electrically coupled to the first source/drain contact and the second source/drain contact.

Abstract: A semiconductor device includes a semiconductor substrate, an isolation feature, gate lines, and a first gate structure. The isolation feature is over the semiconductor substrate and surrounding an active region of the semiconductor substrate. The gate lines extend across the active region of the semiconductor substrate. The first gate structure is over the isolation feature. The first gate structure comprises a first gate line, a second gate line, and a first bridge portion, the first and second gate lines are substantially parallel with the gate lines, and the first bridge portion connects the first gate line to the second gate line.