Patents by Inventor Yun Ling

Yun Ling has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9755334
    Abstract: A retention apparatus for a shielded cable is described. In one embodiment, the apparatus comprises a substrate having a ground; a connector coupled to the substrate; a cable shielded with a conductive material and having an end connectable to the connector to electrically connect with the connector; an electrically conductive material coupled to the ground of the substrate; and a grounding retention mechanism to cause the electrically conductive material to electrically connect the cable to the ground of the substrate by applying a force to the cable shield.
    Type: Grant
    Filed: June 25, 2015
    Date of Patent: September 5, 2017
    Assignee: INTEL CORPORATION
    Inventors: Xiang Li, Yun Ling, Chung-Hao J. Chen, Hao-Han Hsu, Shyamjith Mohan, Kuan-Yu Chen
  • Patent number: 9600653
    Abstract: Providing registration for password/challenge authentication includes receiving an access code or pattern inputted by a user, recording a time message associated with each component of the access code or pattern via a processor, generating a data record in combining each component of the access code or pattern with the associated time message, and storing the data record.
    Type: Grant
    Filed: August 27, 2014
    Date of Patent: March 21, 2017
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Yun-Ling Hilary Cheng, William Hsin-Wei Fu, Min-Tsung Wu, Tony Ping-Chung Yang
  • Patent number: 9596749
    Abstract: Techniques for routing signal traces in a circuit board are described. An example of an electronic device in accordance with the described techniques includes a circuit board comprising a plurality of conductive layers. The conductive layers include a signal layer and a reference plane. The signal layer includes signal traces and the reference plane includes an additional signal trace.
    Type: Grant
    Filed: December 11, 2014
    Date of Patent: March 14, 2017
    Assignee: Intel Corporation
    Inventors: Kuan-Yu Chen, Yun Ling, Mohd Muhaiyiddin Bin Abdullah, Jackson Chung Peng Kong, Chung-Hao Chen, Hao-Han Hsu, Xiang Li
  • Patent number: 9570204
    Abstract: A passive cooling system for a reactor core of a large-scale pressurized water reactor nuclear power plant includes a shield building having an outer wall and a through air inlet arranged on an upper part of the outer wall, a water tank arranged at an upper part of the shield building, a cooling water distribution plate arranged above a top of a containment within the shield building, a spray pipe arranged at an inside of the top of the shield building and having a water inlet end and a water outlet end, wherein the water inlet end is connected to a bottom of the water tank and the water outlet end is extended to be above the cooling water distribution plate, and an air deflector arranged between the shield building and the containment and having an upper end connected to an inside of the top of the shield building.
    Type: Grant
    Filed: December 31, 2013
    Date of Patent: February 14, 2017
    Assignee: Shanghai Nuclear Engineering Research & Design Institute
    Inventors: Mingguang Zheng, Cheng Ye, Honghui Ge, Xiankang Dong, Guoxing Gu, Jinquan Yan, Fuzu Miao, Yong Wang, Yuanwei Ye, Yu Chen, Zufeng Xia, Jian Qiu, Yun Ling
  • Patent number: 9548371
    Abstract: Integrated circuits having nickel silicide contacts and methods for fabricating integrated circuits with nickel silicide contacts are provided. An exemplary method for fabricating an integrated circuit includes providing a semiconductor substrate and forming a nonvolatile memory structure over the semiconductor substrate. The nonvolatile memory structure includes a gate surface. The method further includes depositing a nickel-containing material over the gate surface. Also, the method includes annealing the nonvolatile memory structure and forming a nickel silicide contact on the gate surface from the nickel-containing material.
    Type: Grant
    Filed: April 23, 2014
    Date of Patent: January 17, 2017
    Assignee: GLOBALFOUNDRIES SINGAPORE PTE. LTD.
    Inventors: Jingyan Huang, Chuan Wang, Chim Seng Seet, Yun Ling Tan, Alex See
  • Publication number: 20170003717
    Abstract: In one example a electronic device comprises a body, a receptacle in the body comprising an opening to receive a memory card, wherein the receptacle comprises a first set of connectors configured to connect with pins on a memory card configured in accordance with a first standard and a second set of connectors configured to connect with pins on a memory card configured in accordance with a second standard. Other examples may be described.
    Type: Application
    Filed: February 20, 2015
    Publication date: January 5, 2017
    Applicant: Intel Corporation
    Inventors: Teong Guan YEW, Amit Kumar Srivastava, Feng Yang, Yun Ling
  • Publication number: 20160380370
    Abstract: A retention apparatus for a shielded cable is described. In one embodiment, the apparatus comprises a substrate having a ground; a connector coupled to the substrate; a cable shielded with a conductive material and having an end connectable to the connector to electrically connect with the connector; an electrically conductive material coupled to the ground of the substrate; and a grounding retention mechanism to cause the electrically conductive material to electrically connect the cable to the ground of the substrate by applying a force to the cable shield.
    Type: Application
    Filed: June 25, 2015
    Publication date: December 29, 2016
    Inventors: Xiang Li, Yun Ling, Chung-Hao J. Chen, Hao-Han Hsu, Shyamjith Mohan
  • Patent number: 9462677
    Abstract: Systems and methods provided may involve arranging a first differential pair and a second differential pair and adjusting spacing arrangements between the first differential pair and the second differential pair to minimize crosstalk.
    Type: Grant
    Filed: December 21, 2011
    Date of Patent: October 4, 2016
    Assignee: Intel Corporation
    Inventor: Yun Ling
  • Publication number: 20160263636
    Abstract: A billet (2) is rolled to a rod (3) in a rolling mill. The rod (3) exits the rolling mill with a finishing temperature (TE1). A rear laser measurement device (8) arranged downstream of the rolling mill detects the head end and the speed (v) of the rod (3). The detected speed (v) of the rod (3) is integrated to its length and an instantaneous length (L) of the rod (3) is determined. Dependent on the determined instantaneous length (L) of the rod (3), cutting commands (S) to a rear shears (5) arranged downstream of the rolling mill are provided for cutting the rod (3) in sections (6) of predetermined length (L0). The sections (6) of the rod (3) are cooled down in a cooling bed (7).
    Type: Application
    Filed: March 10, 2015
    Publication date: September 15, 2016
    Inventors: Yun LING, Paul Barry RICHES
  • Patent number: 9391378
    Abstract: Methods and systems to support input output (IO) communications may include an IO connector having a housing with surfaces defining a paddle card region, and a set of compressible contacts extending vertically through the housing into the paddle card region. In addition, an IO interconnect can include a cable portion and at least one end portion coupled to the cable portion. The end portion may include a paddle card having a circuit board with a set of contacts disposed on a bottom surface of the circuit board. The end portion can also include an asymmetric metal shell having a configuration that encloses at least a portion of the paddle card and exposes the set of contacts.
    Type: Grant
    Filed: December 23, 2011
    Date of Patent: July 12, 2016
    Assignee: Intel Corporation
    Inventors: Michael Leddige, Yun Ling, Kuan-Yu Chen, Kai Wang, Xiang Li, Howard Heck
  • Publication number: 20160174361
    Abstract: Techniques for routing signal traces in a circuit board are described. An example of an electronic device in accordance with the described techniques includes a circuit board comprising a plurality of conductive layers. The conductive layers include a signal layer and a reference plane. The signal layer includes signal traces and the reference plane includes an additional signal trace.
    Type: Application
    Filed: December 11, 2014
    Publication date: June 16, 2016
    Applicant: INTEL CORPORATION
    Inventors: Kuan-Yu Chen, Yun Ling, Mohd Muhaiyiddin Bin Abdullah, Jackson Chung Peng Kong, Chung-Hao Chen, Hao-Han Hsu, Xiang Li
  • Patent number: 9318850
    Abstract: In an embodiment, a connector such as an edge connector includes a connector housing, a first set of pins configured within the housing and having first ends to couple to corresponding signal lines of a first circuit board and second ends to couple to corresponding signal lines of a mating connector of a second circuit board, and a conductive material adapted to the housing to reduce interference caused by one or more sources of interference. Other embodiments are described and claimed.
    Type: Grant
    Filed: May 23, 2014
    Date of Patent: April 19, 2016
    Assignee: Intel Corporation
    Inventors: Xiang Li, Hao-Han Hsu, Yun Ling, Gong Ouyang, Kai Xiao, Jiangqi He, Lu-Vong T. Phan, Wei Xu
  • Publication number: 20160087376
    Abstract: Techniques for signal grounding are described herein. The techniques include a conductive element conductively coupled to an exposed ground pad of a circuit board. The conductive element is to conductively couple to a shield of a signaling link, and thereby conductively coupling the shield to the exposed ground pad.
    Type: Application
    Filed: September 22, 2014
    Publication date: March 24, 2016
    Applicant: INTEL CORPORATION
    Inventors: CHUNG-HAO CHEN, YUN LING, XIANG LI
  • Patent number: 9230886
    Abstract: Semiconductor devices with through silicon vias (TSVs) are formed without copper contamination. Embodiments include exposing a passivation layer surrounding a bottom portion of a TSV in a silicon substrate, forming a silicon composite layer over the exposed passivation layer and over a bottom surface of the silicon substrate, forming a hardmask layer over the silicon composite layer and over the bottom surface of the silicon substrate, removing a section of the silicon composite layer around the bottom portion of the TSV using the hardmask layer as a mask, re-exposing the passivation layer, and removing the hardmask layer and the re-exposed passivation layer to expose a contact for the bottom portion of the TSV.
    Type: Grant
    Filed: December 18, 2014
    Date of Patent: January 5, 2016
    Assignee: GLOBALFOUNDRIES SINGAPORE PTE. LTD.
    Inventors: Lup San Leong, Zheng Zou, Alex Kai Hung See, Hai Cong, Xuesong Rao, Yun Ling Tan, Huang Liu
  • Publication number: 20150340817
    Abstract: In an embodiment, a connector such as an edge connector includes a connector housing, a first set of pins configured within the housing and having first ends to couple to corresponding signal lines of a first circuit board and second ends to couple to corresponding signal lines of a mating connector of a second circuit board, and a conductive material adapted to the housing to reduce interference caused by one or more sources of interference. Other embodiments are described and claimed.
    Type: Application
    Filed: May 23, 2014
    Publication date: November 26, 2015
    Inventors: Xiang Li, Hao-Han Hsu, Yun Ling, Gong Ouyang, Kai Xiao, Jiangqi He, Lu-Vong T. Phan, Wei Xu
  • Publication number: 20150311221
    Abstract: Integrated circuits having nickel silicide contacts and methods for fabricating integrated circuits with nickel silicide contacts are provided. An exemplary method for fabricating an integrated circuit includes providing a semiconductor substrate and forming a nonvolatile memory structure over the semiconductor substrate. The nonvolatile memory structure includes a gate surface. The method further includes depositing a nickel-containing material over the gate surface. Also, the method includes annealing the nonvolatile memory structure and forming a nickel silicide contact on the gate surface from the nickel-containing material.
    Type: Application
    Filed: April 23, 2014
    Publication date: October 29, 2015
    Applicant: GLOBALFOUNDRIES Singapore Pte. Ltd.
    Inventors: Jingyan Huang, Chuan Wang, Chim Seng Seet, Yun Ling Tan, Alex See
  • Publication number: 20150280343
    Abstract: In accordance with some embodiments, a high speed connection may be implemented using pogo-pins. The use of pogo-pins may be advantageous because accurate alignment is not required, connection force is generally lower than with other connections and appearance is often highly advantageous. Through the use of a moveable metal shield, an advantageous high speed connection for high speed signaling may be implemented between the two devices.
    Type: Application
    Filed: March 27, 2014
    Publication date: October 1, 2015
    Inventors: Hao-Han Hsu, Yun Ling, Xiang Li
  • Publication number: 20150223321
    Abstract: Systems and methods provided may involve arranging a first differential pair and a second differential pair and adjusting spacing arrangements between the first differential pair and the second differential pair to minimize crosstalk.
    Type: Application
    Filed: December 21, 2011
    Publication date: August 6, 2015
    Inventor: Yun Ling
  • Publication number: 20150171535
    Abstract: According to some embodiments, a SODIMM memory connector comprises a first socket to electrically couple a first SODIMM, and a second socket to electrically couple a second SODIMM, where the first socket is disposed vertically adjacent to the second socket.
    Type: Application
    Filed: December 28, 2011
    Publication date: June 18, 2015
    Inventors: Xiang Li, Chong J. Zhao, Jefferey L. Krieger, Dan Willis, John M. Lynch, Yun Ling
  • Patent number: D746318
    Type: Grant
    Filed: September 4, 2013
    Date of Patent: December 29, 2015
    Assignee: CISCO TECHNOLOGY, INC.
    Inventors: Yun Ling, Xiaochun Liu, Kaijun Pei, Yong Yang