Abstract: A retention apparatus for a shielded cable is described. In one embodiment, the apparatus comprises a substrate having a ground; a connector coupled to the substrate; a cable shielded with a conductive material and having an end connectable to the connector to electrically connect with the connector; an electrically conductive material coupled to the ground of the substrate; and a grounding retention mechanism to cause the electrically conductive material to electrically connect the cable to the ground of the substrate by applying a force to the cable shield.

Abstract: Systems and methods provided may involve arranging a first differential pair and a second differential pair and adjusting spacing arrangements between the first differential pair and the second differential pair to minimize crosstalk.

Abstract: A billet (2) is rolled to a rod (3) in a rolling mill. The rod (3) exits the rolling mill with a finishing temperature (TE1). A rear laser measurement device (8) arranged downstream of the rolling mill detects the head end and the speed (v) of the rod (3). The detected speed (v) of the rod (3) is integrated to its length and an instantaneous length (L) of the rod (3) is determined. Dependent on the determined instantaneous length (L) of the rod (3), cutting commands (S) to a rear shears (5) arranged downstream of the rolling mill are provided for cutting the rod (3) in sections (6) of predetermined length (L0). The sections (6) of the rod (3) are cooled down in a cooling bed (7).

Abstract: Methods and systems to support input output (IO) communications may include an IO connector having a housing with surfaces defining a paddle card region, and a set of compressible contacts extending vertically through the housing into the paddle card region. In addition, an IO interconnect can include a cable portion and at least one end portion coupled to the cable portion. The end portion may include a paddle card having a circuit board with a set of contacts disposed on a bottom surface of the circuit board. The end portion can also include an asymmetric metal shell having a configuration that encloses at least a portion of the paddle card and exposes the set of contacts.

Abstract: Techniques for routing signal traces in a circuit board are described. An example of an electronic device in accordance with the described techniques includes a circuit board comprising a plurality of conductive layers. The conductive layers include a signal layer and a reference plane. The signal layer includes signal traces and the reference plane includes an additional signal trace.

Abstract: In an embodiment, a connector such as an edge connector includes a connector housing, a first set of pins configured within the housing and having first ends to couple to corresponding signal lines of a first circuit board and second ends to couple to corresponding signal lines of a mating connector of a second circuit board, and a conductive material adapted to the housing to reduce interference caused by one or more sources of interference. Other embodiments are described and claimed.

Abstract: Techniques for signal grounding are described herein. The techniques include a conductive element conductively coupled to an exposed ground pad of a circuit board. The conductive element is to conductively couple to a shield of a signaling link, and thereby conductively coupling the shield to the exposed ground pad.

Abstract: Semiconductor devices with through silicon vias (TSVs) are formed without copper contamination. Embodiments include exposing a passivation layer surrounding a bottom portion of a TSV in a silicon substrate, forming a silicon composite layer over the exposed passivation layer and over a bottom surface of the silicon substrate, forming a hardmask layer over the silicon composite layer and over the bottom surface of the silicon substrate, removing a section of the silicon composite layer around the bottom portion of the TSV using the hardmask layer as a mask, re-exposing the passivation layer, and removing the hardmask layer and the re-exposed passivation layer to expose a contact for the bottom portion of the TSV.

Abstract: In an embodiment, a connector such as an edge connector includes a connector housing, a first set of pins configured within the housing and having first ends to couple to corresponding signal lines of a first circuit board and second ends to couple to corresponding signal lines of a mating connector of a second circuit board, and a conductive material adapted to the housing to reduce interference caused by one or more sources of interference. Other embodiments are described and claimed.

Abstract: Integrated circuits having nickel silicide contacts and methods for fabricating integrated circuits with nickel silicide contacts are provided. An exemplary method for fabricating an integrated circuit includes providing a semiconductor substrate and forming a nonvolatile memory structure over the semiconductor substrate. The nonvolatile memory structure includes a gate surface. The method further includes depositing a nickel-containing material over the gate surface. Also, the method includes annealing the nonvolatile memory structure and forming a nickel silicide contact on the gate surface from the nickel-containing material.

Abstract: In accordance with some embodiments, a high speed connection may be implemented using pogo-pins. The use of pogo-pins may be advantageous because accurate alignment is not required, connection force is generally lower than with other connections and appearance is often highly advantageous. Through the use of a moveable metal shield, an advantageous high speed connection for high speed signaling may be implemented between the two devices.

Abstract: Systems and methods provided may involve arranging a first differential pair and a second differential pair and adjusting spacing arrangements between the first differential pair and the second differential pair to minimize crosstalk.

Abstract: According to some embodiments, a SODIMM memory connector comprises a first socket to electrically couple a first SODIMM, and a second socket to electrically couple a second SODIMM, where the first socket is disposed vertically adjacent to the second socket.

Abstract: Semiconductor devices with through silicon vias (TSVs) are formed without copper contamination. Embodiments include exposing a passivation layer surrounding a bottom portion of a TSV in a silicon substrate, forming a silicon composite layer over the exposed passivation layer and over a bottom surface of the silicon substrate, forming a hardmask layer over the silicon composite layer and over the bottom surface of the silicon substrate, removing a section of the silicon composite layer around the bottom portion of the TSV using the hardmask layer as a mask, re-exposing the passivation layer, and removing the hardmask layer and the re-exposed passivation layer to expose a contact for the bottom portion of the TSV.

Abstract: Semiconductor devices with through silicon vias (TSVs) are formed without copper contamination. Embodiments include exposing a passivation layer surrounding a bottom portion of a TSV in a silicon substrate, forming a silicon composite layer over the exposed passivation layer and over a bottom surface of the silicon substrate, forming a hardmask layer over the silicon composite layer and over the bottom surface of the silicon substrate, removing a section of the silicon composite layer around the bottom portion of the TSV using the hardmask layer as a mask, re-exposing the passivation layer, and removing the hardmask layer and the re-exposed passivation layer to expose a contact for the bottom portion of the TSV.

Abstract: Methods and systems to support input output (IO) communications may include an IO connector having a housing with surfaces defining a paddle card region, and a set of compressible contacts extending vertically through the housing into the paddle card region. In addition, an IO interconnect can include a cable portion and at least one end portion coupled to the cable portion. The end portion may include a paddle card having a circuit board with a set of contacts disposed on a bottom surface of the circuit board. The end portion can also include an asymmetric metal shell having a configuration that encloses at least a portion of the paddle card and exposes the set of contacts.

Abstract: Providing registration for password/challenge authentication includes receiving an access code or pattern inputted by a user, recording a time message associated with each component of the access code or pattern via a processor, generating a data record in combining each component of the access code or pattern with the associated time message, and storing the data record.

Abstract: A device for detecting the presence or amount of an analyte in a fluid sample and method thereof, comprises a sample collector and a receiving cup for receiving and holding the sample collector within the receiving cup. The sample collector contains a compressible absorbent member for collecting the fluid sample, and has a first position and a second, locked position within the receiving cup. The absorbent member is uncompressed in the first position and is compressed in the second, locked position. The sample collector or the receiving cup has at least one test element having reagents for detecting the presence or amount of the analyte in the fluid sample.

Abstract: A method (and semiconductor device) of fabricating a semiconductor device utilizes a thermal proximity correction (TPC) technique to reduce the impact of thermal variations during anneal. Prior to actual fabrication, a location of interest (e.g., a transistor) within an integrated circuit design is determined and an effective thermal area around the location is defined. Thermal properties of structures intended to be fabricated within this area are used to calculate an estimated temperature that would be achieved at the location of interest from a given anneal process. If the estimated temperature is below or above a predetermined target temperature (or range), TPC is performed. Various TPC techniques may be performed, such as the addition of dummy cells and/or changing dimensions of the structure to be fabricated at the location of interest (resulting in an modified thermally corrected design, to suppress local variations in device performance caused by thermal variations during anneal.