Patents by Inventor Yun Ling

Yun Ling has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20150137359
    Abstract: Semiconductor devices with through silicon vias (TSVs) are formed without copper contamination. Embodiments include exposing a passivation layer surrounding a bottom portion of a TSV in a silicon substrate, forming a silicon composite layer over the exposed passivation layer and over a bottom surface of the silicon substrate, forming a hardmask layer over the silicon composite layer and over the bottom surface of the silicon substrate, removing a section of the silicon composite layer around the bottom portion of the TSV using the hardmask layer as a mask, re-exposing the passivation layer, and removing the hardmask layer and the re-exposed passivation layer to expose a contact for the bottom portion of the TSV.
    Type: Application
    Filed: December 18, 2014
    Publication date: May 21, 2015
    Inventors: Lup San LEONG, Zheng ZOU, Alex Kai Hung SEE, Hai CONG, Xuesong RAO, Yun Ling TAN, Huang LIU
  • Patent number: 8940637
    Abstract: Semiconductor devices with through silicon vias (TSVs) are formed without copper contamination. Embodiments include exposing a passivation layer surrounding a bottom portion of a TSV in a silicon substrate, forming a silicon composite layer over the exposed passivation layer and over a bottom surface of the silicon substrate, forming a hardmask layer over the silicon composite layer and over the bottom surface of the silicon substrate, removing a section of the silicon composite layer around the bottom portion of the TSV using the hardmask layer as a mask, re-exposing the passivation layer, and removing the hardmask layer and the re-exposed passivation layer to expose a contact for the bottom portion of the TSV.
    Type: Grant
    Filed: July 5, 2012
    Date of Patent: January 27, 2015
    Assignee: Globalfoundries Singapore Pte. Ltd.
    Inventors: Lup San Leong, Zheng Zou, Alex Kai Hung See, Hai Cong, Xuesong Rao, Yun Ling Tan, Huang Liu
  • Publication number: 20140377968
    Abstract: Methods and systems to support input output (IO) communications may include an IO connector having a housing with surfaces defining a paddle card region, and a set of compressible contacts extending vertically through the housing into the paddle card region. In addition, an IO interconnect can include a cable portion and at least one end portion coupled to the cable portion. The end portion may include a paddle card having a circuit board with a set of contacts disposed on a bottom surface of the circuit board. The end portion can also include an asymmetric metal shell having a configuration that encloses at least a portion of the paddle card and exposes the set of contacts.
    Type: Application
    Filed: December 23, 2011
    Publication date: December 25, 2014
    Inventors: Michael Leddige, Yun Ling, Kuan-Yu Chen, Kai Wang, Xiang Li, Howard Heck
  • Publication number: 20140373119
    Abstract: Providing registration for password/challenge authentication includes receiving an access code or pattern inputted by a user, recording a time message associated with each component of the access code or pattern via a processor, generating a data record in combining each component of the access code or pattern with the associated time message, and storing the data record.
    Type: Application
    Filed: August 27, 2014
    Publication date: December 18, 2014
    Inventors: Yun-Ling Hilary Cheng, William Hsin-Wei Fu, Min-Tsung Wu, Tony Ping-Chung Yang
  • Patent number: 8871155
    Abstract: A device for detecting the presence or amount of an analyte in a fluid sample and method thereof, comprises a sample collector and a receiving cup for receiving and holding the sample collector within the receiving cup. The sample collector contains a compressible absorbent member for collecting the fluid sample, and has a first position and a second, locked position within the receiving cup. The absorbent member is uncompressed in the first position and is compressed in the second, locked position. The sample collector or the receiving cup has at least one test element having reagents for detecting the presence or amount of the analyte in the fluid sample.
    Type: Grant
    Filed: November 13, 2006
    Date of Patent: October 28, 2014
    Assignee: Alere Switzerland GmbH
    Inventors: Yuzhang Wu, Yun Ling, Jielin Dai
  • Patent number: 8860142
    Abstract: A method (and semiconductor device) of fabricating a semiconductor device utilizes a thermal proximity correction (TPC) technique to reduce the impact of thermal variations during anneal. Prior to actual fabrication, a location of interest (e.g., a transistor) within an integrated circuit design is determined and an effective thermal area around the location is defined. Thermal properties of structures intended to be fabricated within this area are used to calculate an estimated temperature that would be achieved at the location of interest from a given anneal process. If the estimated temperature is below or above a predetermined target temperature (or range), TPC is performed. Various TPC techniques may be performed, such as the addition of dummy cells and/or changing dimensions of the structure to be fabricated at the location of interest (resulting in an modified thermally corrected design, to suppress local variations in device performance caused by thermal variations during anneal.
    Type: Grant
    Filed: October 10, 2012
    Date of Patent: October 14, 2014
    Assignee: Globalfoundries Singapore Pte. Ltd.
    Inventors: Debora Chyiu Hyia Poon, Alex K H See, Francis Benistant, Benjamin Colombeau, Yun Ling Tan, Mei Sheng Zhou, Liang Choo Hsia
  • Patent number: 8853796
    Abstract: A device includes a substrate with a device region surrounded by an isolation region, in which the device region includes edge portions along a width of the device region and a central portion. The device further includes a gate layer disposed on the substrate over the device region, in which the gate layer includes a graded thickness in which the gate layer at edge portions of the device region has a thickness TE that is different from a thickness TC at the central portion of the device region.
    Type: Grant
    Filed: May 19, 2011
    Date of Patent: October 7, 2014
    Assignees: GLOBALFOUNDIERS Singapore Pte. Ltd.
    Inventors: Young Way Teh, Michael V. Aquilino, Arifuzzaman (Arif) Sheikh, Yun Ling Tan, Hao Zhang, Deleep R. Nair, Jinghong H. (John) Li
  • Publication number: 20140287409
    Abstract: Compositions and methods related to assessing the risk of cancer, such as breast cancer, lung cancer and bladder cancer, through analyzing the length of telomeres, such as chromosome 9p, 15p, and/or Xp telomere, such as the short arm of the 9p, 15p, and/or Xp telomere.
    Type: Application
    Filed: March 14, 2014
    Publication date: September 25, 2014
    Applicant: Georgetown University
    Inventor: Yun-Ling Zheng
  • Patent number: 8828858
    Abstract: Interlayer dielectric gap fill processes are enhanced by forming gate spacers with a tapered profile. Embodiments include forming a gate electrode on a substrate, depositing a spacer material over the gate electrode and substrate, the spacer layer having a first surface nearest the gate electrode and substrate, a second surface furthest from the gate electrode and substrate, and a continuously increasing etch rate from the first surface to the second surface, and etching the spacer layer to form a spacer on each side of the gate electrode. Embodiments further include forming the spacer layer by depositing a spacer material and continuously decreasing the density of the spacer material during deposition or depositing a carbon-containing spacer material and causing a gradient of carbon content in the spacer layer.
    Type: Grant
    Filed: January 19, 2012
    Date of Patent: September 9, 2014
    Assignee: GLOBALFOUNDRIES Singapore Pte. Ltd.
    Inventors: Xuesong Rao, Chim Seng Seet, Hai Cong, Zheng Zou, Alex See, Yun Ling Tan, Wen Zhan Zhou, Lup San Leong
  • Patent number: 8826029
    Abstract: Providing registration for password/challenge authentication includes receiving an access code or pattern inputted by a user, recording a time message associated with each component of the access code or pattern via a processor, generating a data record in combining each component of the access code or pattern with the associated time message, and storing the data record.
    Type: Grant
    Filed: September 21, 2012
    Date of Patent: September 2, 2014
    Assignee: International Business Machines Corporation
    Inventors: Yun-Ling Hilary Cheng, William Hsin-Wei Fu, Min-Tsung Wu, Tony Ping-Chung Yang
  • Publication number: 20140112427
    Abstract: A passive cooling system for a reactor core of a large-scale pressurized water reactor nuclear power plant includes a shield building having an outer wall and a through air inlet arranged on an upper part of the outer wall, a water tank arranged at an upper part of the shield building, a cooling water distribution plate arranged above a top of a containment within the shield building, a spray pipe arranged at an inside of the top of the shield building and having a water inlet end and a water outlet end, wherein the water inlet end is connected to a bottom of the water tank and the water outlet end is extended to be above the cooling water distribution plate, and an air deflector arranged between the shield building and the containment and having an upper end connected to an inside of the top of the shield building.
    Type: Application
    Filed: December 31, 2013
    Publication date: April 24, 2014
    Applicant: SHANGHAI NUCLEAR ENGINEERING RESEARCH & DESIGN INSTITUTE
    Inventors: Mingguang ZHENG, Cheng YE, Honghui GE, Xiankang DONG, Guoxing GU, Jinquan YAN, Fuzu MIAO, Yong WANG, Yuanwei YE, Yu CHEN, Zufeng XIA, Jian QIU, Yun LING
  • Publication number: 20140008810
    Abstract: Semiconductor devices with through silicon vias (TSVs) are formed without copper contamination. Embodiments include exposing a passivation layer surrounding a bottom portion of a TSV in a silicon substrate, forming a silicon composite layer over the exposed passivation layer and over a bottom surface of the silicon substrate, forming a hardmask layer over the silicon composite layer and over the bottom surface of the silicon substrate, removing a section of the silicon composite layer around the bottom portion of the TSV using the hardmask layer as a mask, re-exposing the passivation layer, and removing the hardmask layer and the re-exposed passivation layer to expose a contact for the bottom portion of the TSV.
    Type: Application
    Filed: July 5, 2012
    Publication date: January 9, 2014
    Applicant: GLOBALFOUNDRIES Singapore Pte. Ltd.
    Inventors: Lup San Leong, Zheng Zou, Alex Kai Hung See, Hai Cong, Xuesong Rao, Yun Ling Tan, Huang Liu
  • Patent number: 8531044
    Abstract: An epoxy resin composition for encapsulating a semiconductor device and a semiconductor device, the composition including an epoxy resin, a curing agent, a curing accelerator, an inorganic filler, and an additive, wherein the epoxy resin includes an epoxy resin represented by Formula 1:
    Type: Grant
    Filed: December 28, 2011
    Date of Patent: September 10, 2013
    Assignee: Cheil Industries, Inc.
    Inventors: Seung Han, Yun Ling
  • Publication number: 20130187202
    Abstract: Interlayer dielectric gap fill processes are enhanced by forming gate spacers with a tapered profile. Embodiments include forming a gate electrode on a substrate, depositing a spacer material over the gate electrode and substrate, the spacer layer having a first surface nearest the gate electrode and substrate, a second surface furthest from the gate electrode and substrate, and a continuously increasing etch rate from the first surface to the second surface, and etching the spacer layer to form a spacer on each side of the gate electrode. Embodiments further include forming the spacer layer by depositing a spacer material and continuously decreasing the density of the spacer material during deposition or depositing a carbon-containing spacer material and causing a gradient of carbon content in the spacer layer.
    Type: Application
    Filed: January 19, 2012
    Publication date: July 25, 2013
    Applicant: GLOBALFOUNDRIES Singapore Pte. Ltd.
    Inventors: Xuesong Rao, Chim Seng Seet, Hai Cong, Zheng Zou, Alex See, Yun Ling Tan, Wen Zhan Zhou, Lup San Leong
  • Patent number: 8492236
    Abstract: Interlayer dielectric gap fill processes are enhanced by forming gate spacers with a step-like or tapered profile. Embodiments include forming a gate electrode on a substrate, depositing a spacer material over the gate electrode, etching the spacer material to form a first spacer on each side of the gate electrode, and pulling back the first spacers to form second spacers which have a step-like profile. Embodiments further include depositing a second spacer material over the gate electrode and the second spacers, and etching the second spacer material to form a third spacer on each second spacer, the second and third spacers forming an outwardly tapered composite spacer.
    Type: Grant
    Filed: January 12, 2012
    Date of Patent: July 23, 2013
    Assignee: GLOBALFOUNDRIES Singapore Pte. Ltd.
    Inventors: Xuesong Rao, Chim Seng Seet, Hai Cong, Zheng Zou, Alex See, Yun Ling Tan, Wen Zhan Zhou, Lup San Leong, Huang Liu
  • Publication number: 20130181259
    Abstract: Interlayer dielectric gap fill processes are enhanced by forming gate spacers with a step-like or tapered profile. Embodiments include forming a gate electrode on a substrate, depositing a spacer material over the gate electrode, etching the spacer material to form a first spacer on each side of the gate electrode, and pulling back the first spacers to form second spacers which have a step-like profile. Embodiments further include depositing a second spacer material over the gate electrode and the second spacers, and etching the second spacer material to form a third spacer on each second spacer, the second and third spacers forming an outwardly tapered composite spacer.
    Type: Application
    Filed: January 12, 2012
    Publication date: July 18, 2013
    Inventors: Xuesong Rao, Chim Seng Seet, Hai Cong, Zheng Zou, Alex See, Yun Ling Tan, Wen Zhan Zhou, Lup San Leong, Huang Liu
  • Publication number: 20120292719
    Abstract: A device includes a substrate with a device region surrounded by an isolation region, in which the device region includes edge portions along a width of the device region and a central portion. The device further includes a gate layer disposed on the substrate over the device region, in which the gate layer includes a graded thickness in which the gate layer at edge portions of the device region has a thickness TE that is different from a thickness TC at the central portion of the device region.
    Type: Application
    Filed: May 19, 2011
    Publication date: November 22, 2012
    Applicants: INTERNATIONAL BUSINESS MACHINES CORPORATION, GLOBALFOUNDRIES SINGAPORE PTE. LTD.
    Inventors: Young Way TEH, Michael V. AQUILINO, Arifuzzaman (Arif) SHEIKH, Yun Ling TAN, Hao ZHANG, Deleep R. NAIR, Jinghong H. (John) LI
  • Publication number: 20120270947
    Abstract: Disclosed are compositions and methods related to assessing the risk of cancer, such as breast cancer, through analyzing the length of telomeres, such as chromosome 9p telomere, such as the short arm of the 9p telomere. If the 9p arm is shorter than normal, the risk of cancer is increased.
    Type: Application
    Filed: October 17, 2011
    Publication date: October 25, 2012
    Applicant: Georgetown University
    Inventor: Yun-Ling Zheng
  • Patent number: 8293544
    Abstract: A method (and semiconductor device) of fabricating a semiconductor device utilizes a thermal proximity correction (TPC) technique to reduce the impact of thermal variations during anneal. Prior to actual fabrication, a location of interest (e.g., a transistor) within an integrated circuit design is determined and an effective thermal area around the location is defined. Thermal properties of structures intended to be fabricated within this area are used to calculate an estimated temperature that would be achieved at the location of interest from a given anneal process. If the estimated temperature is below or above a predetermined target temperature (or range), TPC is performed. Various TPC techniques may be performed, such as the addition of dummy cells and/or changing dimensions of the structure to be fabricated at the location of interest (resulting in an modified thermally corrected design, to suppress local variations in device performance caused by thermal variations during anneal.
    Type: Grant
    Filed: July 28, 2008
    Date of Patent: October 23, 2012
    Assignee: GlobalFoundries Singapore Pte. Ltd.
    Inventors: Debora Chyiu Hyia Poon, Alex Kh See, Francis Benistant, Benjamin Colombeau, Yun Ling Tan, Mei Sheng Zhou, Liang Choo Hsia
  • Patent number: 8292655
    Abstract: Embodiments of the invention use a small piece of flex or rigid PCB as the cable plug. The wires of the cable are soldered onto the pads on the PCB with the pads so arranged that all the ground pads are tied together without needing a separate grounding bar. The signal and GND pads are so aligned such that minimum strip length is required for soldering and the symmetry of the differential signals is maintained.
    Type: Grant
    Filed: April 1, 2011
    Date of Patent: October 23, 2012
    Assignee: Intel Corporation
    Inventors: Yun Ling, Daniel T. Tong