Abstract: The present invention provides compositions comprising chimeric polypeptides that bind to free ubiquitin proteins or free ubiquitin-like proteins with high affinity, as well as chimeric polypeptides that bind to both free and conjugated ubiquitin proteins or free and conjugated ubiquitin-like proteins, and methods of using the chimeric polypeptides to determine the amount of free or total ubiquitin or free or total ubiquitin-like proteins in various types of samples.

Abstract: Disclosed is a semiconductor package comprising a first semiconductor chip, a second semiconductor chip on a first surface of the first semiconductor chip, and a plurality of conductive pillars on the first surface of the first semiconductor chip and adjacent to at least one side of the second semiconductor chip. The first semiconductor chip includes a first circuit layer adjacent to the first surface of the first semiconductor chip. The second semiconductor chip and the plurality of conductive pillars are connected to the first surface of the first semiconductor chip.

Abstract: A semiconductor package includes a substrate and an interposer disposed on the substrate. The interposer comprises a first surface facing the substrate and a second surface facing away from the substrate. A first logic semiconductor chip is disposed on the first surface of the interposer and is spaced apart from the substrate in a first direction orthogonal to an upper surface of the substrate. A first memory package is disposed on the second surface of the interposer. A second memory package is disposed on the second surface of the interposer and is spaced apart from the first memory package in a second direction that is parallel to the upper surface of the substrate. A first heat transfer unit is disposed on a surface of the substrate facing the first logic semiconductor chip. The first heat transfer unit is spaced apart from the first logic semiconductor chip in the first direction.

Abstract: A semiconductor package includes: a first thermal pillar disposed on a package substrate, and having an opening; a first chip stack disposed on the package substrate and in the opening of the first thermal pillar, and including a first lateral surface; a semiconductor chip disposed on the package substrate and in the opening, wherein the semiconductor chip is spaced apart from the first chip stack; and a first heat transfer film disposed between the first thermal pillar and the first lateral surface of the first chip stack.

Abstract: A semiconductor package includes a package substrate, an interposer on the package substrate, and a first semiconductor device and a second semiconductor device on the interposer, the first and second semiconductor devices connected to each other by the interposer, wherein at least one of the first semiconductor device and the second semiconductor device includes an overhang portion protruding from a sidewall of the interposer.

Abstract: An interposer includes: a base substrate; an interconnection structure on a top surface of the base substrate and including a metal interconnection pattern; an upper passivation layer on the interconnection structure and having compressive stress; a lower passivation layer under a bottom surface of base substrate, the lower passivation layer having compressive stress that is less than the compressive stress of the upper passivation layer; a lower conductive layer under the lower passivation layer; and a through electrode penetrating the base substrate and the lower passivation layer. The through electrode electrically connects the lower conductive layer to the metal interconnection pattern of the interconnection structure.

Abstract: A semiconductor package may include a package substrate, a first interposer substrate mounted on the package substrate, and a first semiconductor chip disposed on the first interposer substrate. The first interposer substrate may include a first base layer, a second base layer disposed on the first base layer, circuit patterns provided in each of the first base layer and the second base layer, and an integrated device embedded in the first base layer and connected to at least one of the circuit patterns. A top surface of the first base layer may contact a bottom surface of the second base layer.

Abstract: A semiconductor package includes upper and lower semiconductor chip packages, and a redistribution wiring layer pattern interposed between the packages. The lower package includes a molding layer in which at least one chip is embedded, and has a top surface and an inclined sidewall surface along which the redistribution wiring layer pattern is formed. The upper and lower packages are electrically connected to through the redistribution wiring layer pattern. A first package may be formed by a wafer level packaging technique and may include a redistribution wiring layer as a substrate, a semiconductor chip disposed on the redistribution wiring layer, and a molding layer on which the lower package, redistribution wiring layer pattern and upper package are disposed.

Abstract: A semiconductor package includes a base package substrate, a first semiconductor chip, and a second semiconductor chip. The base package substrate includes a redistribution region where a redistribution layer is provided, a plurality of vertical conductive vias connected to the redistribution layer, and a recess region recessed from an upper surface of the redistribution region. The base package substrate further includes an interposer in the recess region, the interposer comprising a substrate, a plurality of upper pads disposed at an upper surface of the substrate, and plurality of through electrodes respectively connected to the plurality of upper pads to pass through the substrate. The first semiconductor chip and second semiconductor chip, each include a plurality of conductive interconnection terminals respectively connected to the plurality of upper pads and the vertical conductive vias exposed at the upper surface of the redistribution region.

Abstract: A method and apparatus are provided for controlling a data rate in a mobile communication system. The method includes changing an offset from a first offset used in a previous packet to a second offset determined based on whether or not the previous packet is successfully received by a second apparatus; determining whether or not a second channel quality in which the second offset is applied is within a range from a minimum quality to a maximum quality; if it is determined that the second channel quality is not within the range, determining that the offset is maintained as the first offset in a current packet; and transmitting, to the second apparatus, the current packet according to a first channel quality in which the first offset is applied.

Abstract: A camera unit and method of control are described. The camera unit has a camera flash sub-unit configurable to emit flash light having an adjustable characteristic. A camera sensor sub-unit generates raw color data when exposed to light for processing into a digital image. The camera unit also includes a camera controller for coordinating operation of the camera flash sub-unit and the camera sensor sub-unit. The camera controller monitors one or more ambient light characteristics in a vicinity of the camera unit. Prior to receiving a command instructing the camera unit to generate the digital image, the camera controller repeatedly configures the camera flash sub-unit based on the monitored ambient light characteristics to adjust the characteristics of the emitted flash light. Once the camera controller receives the command, the camera sensor sub-unit is instructed to expose an image sensor using the pre-adjusted camera flash light to increase illumination.

Abstract: The present invention relates to an asymmetric elliptical chainring for a clipless pedal, wherein a slope at each imaginary point of a first to second elliptical section increases counterclockwise, a slope at each imaginary point of a third elliptical section decreases counterclockwise, a virtual center line in a longitudinal direction of a crank arm is located so as to have a set angle in the counterclockwise direction from a starting point of the first elliptical section, the starting point of the first elliptical section is the shortest distance from a center of an asymmetric ellipse, has a curve of a first set curvature or less, and forms a first angular section from the starting point of the first elliptical section, a start point of the second elliptical section meets an end point of the first elliptical section located within a first near transition section, the end point of the second elliptical section is the longest distance from the center of the asymmetric ellipse, a curvature of the second ellipt

Abstract: A method and apparatus are provided for controlling a data rate in a mobile communication system. The method includes changing an offset from a first offset used in a previous packet to a second offset determined based on whether or not the previous packet is successfully received by a second apparatus; determining whether or not a second channel quality in which the second offset is applied is within a range from a minimum quality to a maximum quality; if it is determined that the second channel quality is not within the range, determining that the offset is maintained as the first offset in a current packet; and transmitting, to the second apparatus, the current packet according to a first channel quality in which the first offset is applied.

Abstract: The present invention provides compositions comprising chimeric polypeptides that bind to free ubiquitin proteins or free ubiquitin-like proteins with high affinity, as well as chimeric polypeptides that bind to both free and conjugated ubiquitin proteins or free and conjugated ubiquitin-like proteins, and methods of using the chimeric polypeptides to determine the amount of free or total ubiquitin or free or total ubiquitin-like proteins in various types of samples.

Abstract: Provided is a substrate cleaning apparatus including: a cleaning bath configured to accommodate a substrate having a first surface and a second surface; a substrate support configured to support the substrate; first and second nozzle bars provided in the cleaning bath to be rotatable in a plane parallel with the substrate, each of the first and the second nozzle bars including a passage; a plurality of nozzles provided along a longitudinal direction of each of the first and the second nozzle bars and configured to spray the cleaning solution from the passage of each of the first and the second nozzle bars to the substrate; and first and second brushes, the first brush provided on a first side of the substrate and configured to clean the first surface and the second brush provided on a second side of the substrate and configured to clean the second surface of the substrate.

Abstract: A semiconductor package includes upper and lower semiconductor chip packages, and a redistribution wiring layer pattern interposed between the packages. The lower package includes a molding layer in which at least one chip is embedded, and has a top surface and an inclined sidewall surface along which the redistribution wiring layer pattern is formed. The upper and lower packages are electrically connected to through the redistribution wiring layer pattern. A first package may be formed by a wafer level packaging technique and may include a redistribution wiring layer as a substrate, a semiconductor chip disposed on the redistribution wiring layer, and a molding layer on which the lower package, redistribution wiring layer pattern and upper package are disposed.

Abstract: A method of forming patterns for a semiconductor device includes preparing a hardmask composition including a carbon allotrope, a spin-on hardmask (SOH) material, an aromatic ring-containing polymer, and a solvent, applying the hardmask composition to an etching target layer, forming a hardmask by heat-treating the applied hardmask composition, forming a photoresist pattern on the hardmask, forming a hardmask pattern by etching the hardmask using the photoresist pattern as an etching mask, and forming an etched pattern by etching the etching target layer using the hardmask pattern as an etching mask.

Abstract: The present invention provides compositions comprising chimeric polypeptides that bind to free ubiquitin proteins or free ubiquitin-like proteins with high affinity, as well as chimeric polypeptides that bind to both free and conjugated ubiquitin proteins or free and conjugated ubiquitin-like proteins, and methods of using the chimeric polypeptides to determine the amount of free or total ubiquitin or free or total ubiquitin-like proteins in various types of samples.

Abstract: A crosstalk processing module configured to process a crosstalk of an image signal includes a correction element generation unit, a storage, and a crosstalk correction check unit. The correction element generation unit receives the image signal and input information associated with at least a size of the image signal and generates seed values and correction parameters which are used to correct the crosstalk, based on the input information and a representative channel image signal obtained by separating the image signal with respect to color. The storage stores the seed values and the correction parameters. The crosstalk correction check unit receives the image signal, receives the seed values and the correction parameters from the storage, corrects the crosstalk, and outputs a final image signal and pass/fail information indicating a pass or fail of the correction of the crosstalk based on a plurality of reference values.

Abstract: A method and apparatus are provided for controlling a data rate in a mobile communication system. The method includes changing an offset from a first offset used in a previous packet to a second offset determined based on whether or not the previous packet is successfully received by a second apparatus; determining whether or not a second channel quality in which the second offset is applied is within a range from a minimum quality to a maximum quality; if it is determined that the second channel quality is not within the range, determining that the offset is maintained as the first offset in a current packet; and transmitting, to the second apparatus, the current packet according to a first channel quality in which the first offset is applied.