Abstract: A high efficient photovoltaic module with cut cells including: the surface glass layer, the upper encapsulation layer, the solar cell string layer, the lower encapsulation layer, and the back plate. The solar cell string layer includes a plurality of solar cell strings, each solar cell string including a plurality of solar cells connected by using a first electric conductor and a second electric conductor. The plurality of solar cells is connected in series by the first electric conductor on front sides. The plurality of solar cells is connected in series by the second electric conductor on back sides.

Abstract: A bifacial double glass solar module including: the upper glass layer, the upper encapsulation layer, the cell layer, the lower encapsulation layer, and the lower glass layer. The upper glass layer, the upper encapsulation layer, the cell layer, the lower encapsulation layer, and the lower glass layer are disposed sequentially from top to bottom. The cell layer includes a plurality of double-sided cells connected in series by a solder strip. The upper glass layer is provided with a first anti-reflection film layer on the upper surface and a first up-conversion thin film layer on the lower surface. The lower glass layer is provided with a second up-conversion thin film layer on the upper surface and a second anti-reflection film layer on the lower surface.

Abstract: Techniques for intelligently predicting bundles of replacement parts. A plurality of maintenance events for a plurality of replacement parts are determined based on historical data related to the plurality of replacement parts. Each maintenance event of the plurality of maintenance events corresponds with one or more of the replacement parts. A plurality of clusters of replacement parts are generated based on the plurality of maintenance events. A plurality of bundles of replacement parts are predicted based on the clusters. Each bundle includes a plurality of replacement parts.

Abstract: The present invention is directed to a method for controlling the outlet temperature of an oil injected compressor or vacuum pump comprising a compressor or vacuum element provided with a gas inlet, an element outlet, and an oil inlet, said method comprising the steps of: measuring the outlet temperature at the element outlet; and controlling the position of a regulating valve in order to regulate the flow of oil flowing through a cooling unit connected to said oil inlet; whereby the step of controlling the position of the regulating valve involves applying a fuzzy logic algorithm on the measured outlet temperature; and in that the method further comprises the step of controlling the speed of a fan cooling the oil flowing through the cooling unit by applying the fuzzy logic algorithm and further based on the position of the regulating valve.

Abstract: A power control circuit includes a first power supply circuit configured to supply power to a universal serial bus upon a motherboard is turned on. When the motherboard is turned on, a first power source outputs a first voltage to a first input terminal of a double diode of the first power supply circuit, a second power source outputs a second voltage to a second input terminal of the double diode, an output terminal of the double diode outputs a first voltage, the first voltage controls the first electronic switch to switch on, and a third power supply outputs a second voltage through a first electronic switch of the first power supply circuit to provide power to the universal serial bus.

Abstract: Systems and methods are disclosed for identifying transitions within media content items. In one implementation, a processing device process a first media content item, the first media content item being associated with a transition, to identify one or more characteristics associated with the transition. The processing device processes a second media content item to identify at least one of the one or more characteristics at a chronological interval of the second media content item. The processing device receives a sponsored content item. The processing device provides, during a presentation of the second media content item, the sponsored content item at the chronological interval.

Abstract: A computer-implemented method for determining online content insertion points in an online publication is provided. The method is implemented using a break point identifying (“BPI”) computer device in communication with a memory device. The method includes receiving a candidate online publication that includes a plurality of audio segments, identifying one or more of the plurality of audio segments, determining at least one break candidate within the candidate online publication based on the identification of one or more of the plurality of audio segments, determining at least one content insertion point with the candidate online publication based on the at least one break candidate. Each content insertion point represents a point in the candidate online publication for presenting online content, and store the at least one content insertion point in association with the candidate online publication.

Abstract: A cascode amplifier including a common-source device and a common-gate device formed utilizing different processing parameters to separately optimize performance of the common-source device and common-gate device.

Abstract: Approaches for LDMOS devices are provided. A method of forming a semiconductor structure includes forming a gate dielectric including a first portion having a first uniform thickness, a second portion having a second uniform thickness different than the first uniform thickness, and a transition portion having tapered surface extending from the first portion to the second portion. The gate dielectric is formed on a planar upper surface of a substrate. The tapered surface is at an acute angle relative to the upper surface of the substrate.

Abstract: Systems and methods are disclosed for identifying transitions within media content items. In one implementation, a processing device process a first media content item, the first media content item being associated with a transition, to identify one or more characteristics associated with the transition. The processing device processes a second media content item to identify at least one of the one or more characteristics at a chronological interval of the second media content item. The processing device receives a sponsored content item. The processing device provides, during a presentation of the second media content item, the sponsored content item at the chronological interval.

Abstract: The instant disclosure is directed to solution phase fragment coupling methods for preparing etelcalcetide and its pharmaceutically acceptable salts.

Abstract: A semiconductor structure and method of manufacture and, more particularly, a field effect transistor that has a body contact and method of manufacturing the same is provided. The structure includes a device having a raised source region of a first conductivity type and an active region below the raised source region extending to a body of the device. The active region has a second conductivity type different than the first conductivity type. A contact region is in electric contact with the active region. The method includes forming a raised source region over an active region of a device and forming a contact region of a same conductivity type as the active region, wherein the active region forms a contact body between the contact region and a body of the device.

Abstract: Disclosed are methods that employ a mask with openings arranged in a pattern of elongated trenches and holes of varying widths to achieve a linearly graded conductivity level. These methods can be used to form a lateral double-diffused metal oxide semiconductor field effect transistor (LDMOSFET) with a drain drift region having an appropriate type conductivity at a level that increases essentially linearly from the body region to the drain region. Furthermore, these methods also provide for improve manufacturability in that multiple instances of this same pattern can be used during a single dopant implant process to implant a first dopant with a first type (e.g., N-type) conductivity into the drain drift regions of both first and second type LDMOSFETs (e.g., N and P-type LDMOSFETs, respectively). In this case, the drain drift region of a second type LDMOSFET can subsequently be uniformly counter-doped. Also disclosed are the resulting semiconductor structures.

Abstract: A method of forming a semiconductor structure in a semiconductor-on-insulator (SOI) substrate and semiconductor structure so formed are provided. The SOI substrate includes a semiconductor layer; a bulk semiconductor region underlying the semiconductor layer; and an insulation layer between the two. The structure includes first and second openings each having sidewalls, each of the first opening and the second opening formed substantially simultaneously and extending from a top surface of the semiconductor layer through the semiconductor layer and through the insulation layer to the conductive region; an insulating material adapted to provide electrical insulation to at least a portion of the side walls of the first opening; a semiconductor material at least partially filling the first opening, the semiconductor material defining an ohmic contact trench providing electrical contact with the semiconductor region; and an insulating material disposed in the second opening and defining a device isolation trench.

Abstract: Disclosed are methods that employ a mask with openings arranged in a pattern of elongated trenches and holes of varying widths to achieve a linearly graded conductivity level. These methods can be used to form a lateral double-diffused metal oxide semiconductor field effect transistor (LDMOSFET) with a drain drift region having an appropriate type conductivity at a level that increases essentially linearly from the body region to the drain region. Furthermore, these methods also provide for improve manufacturability in that multiple instances of this same pattern can be used during a single dopant implant process to implant a first dopant with a first type (e.g., N-type) conductivity into the drain drift regions of both first and second type LDMOSFETs (e.g., N and P-type LDMOSFETs, respectively). In this case, the drain drift region of a second type LDMOSFET can subsequently be uniformly counter-doped. Also disclosed are the resulting semiconductor structures.

Abstract: Various embodiments include structures for field effect transistors (FETs). In various embodiments, a structure for a FET includes: a deep n-type well; a shallow n-type well within the deep n-type well; and a shallow trench isolation (STI) region within the shallow n-type well, the STI region including: a first section having a first depth within the shallow n-type well as measured from an upper surface of the shallow n-type well, and a second section contacting and overlying the first section, the second section having a second depth within the shallow n-type well as measured from the upper surface of the shallow n-type well.

Abstract: Approaches for LDMOS devices are provided. A method of forming a semiconductor structure includes forming a gate dielectric including a first portion having a first uniform thickness, a second portion having a second uniform thickness different than the first uniform thickness, and a transition portion having tapered surface extending from the first portion to the second portion. The gate dielectric is formed on a planar upper surface of a substrate. The tapered surface is at an acute angle relative to the upper surface of the substrate.

Abstract: A method of forming a semiconductor structure in a semiconductor-on-insulator (SOI) substrate and semiconductor structure so formed are provided. The SOI substrate includes a semiconductor layer; a bulk semiconductor region underlying the semiconductor layer; and an insulation layer between the two. The structure includes first and second openings each having sidewalls, each of the first opening and the second opening formed substantially simultaneously and extending from a top surface of the semiconductor layer through the semiconductor layer and through the insulation layer to the conductive region; an insulating material adapted to provide electrical insulation to at least a portion of the side walls of the first opening; a semiconductor material at least partially filling the first opening, the semiconductor material defining an ohmic contact trench providing electrical contact with the semiconductor region; and an insulating material disposed in the second opening and defining a device isolation trench.

Abstract: Semiconductor structures and methods of manufacture are disclosed herein. Specifically, disclosed herein are methods of manufacturing a high-voltage metal-oxide-semiconductor field-effect transistor and respective structures. A method includes forming a field-effect transistor (FET) on a substrate in a FET region, forming a high-voltage FET (HVFET) on a dielectric stack over a over lightly-doped diffusion (LDD) drain in a HVFET region, and forming an NPN on the substrate in an NPN region.

Abstract: Low leakage, high frequency devices and methods of manufacture are disclosed. The method of forming a device includes implanting a lateral diffusion drain implant in a substrate by a blanket implantation process. The method further includes forming a self-aligned tapered gate structure on the lateral diffusion drain implant. The method further includes forming a halo implant in the lateral diffusion drain implant, adjacent to the self-aligned tapered gate structure and at least partially under a source region of the self-aligned tapered gate structure.