Abstract: A semiconductor device structure and a method for forming a semiconductor device structure are provided. The semiconductor device structure includes a metal gate stack over a substrate and an epitaxial structure over the substrate. The semiconductor device structure also includes a conductive contact electrically connected to the epitaxial structure. A topmost surface of the metal gate stack is vertically disposed between a topmost surface of the conductive contact and a bottommost surface of the conductive contact. The semiconductor device structure further includes a first conductive via electrically connected to the metal gate stack. The topmost surface of the conductive contact is vertically disposed between a topmost surface of the first conductive via and a bottommost surface of the first conductive via. In addition, the semiconductor device structure includes a second conductive via electrically connected to the conductive contact.

Abstract: One aspect of the present disclosure pertains to a semiconductor structure. The semiconductor structure includes a first circuit area having: an active region extending lengthwise along a first direction, the active region includes a channel region between source/drain (S/D) features and a gate over the channel region, a dielectric structure over and surrounding the active region, a metal contact penetrating through a top surface of the dielectric structure to land on one of the S/D features, and a first via landing on the metal contact. The semiconductor structure includes a second circuit area having: the dielectric structure, a feedthrough via penetrating through the top surface of the dielectric structure and a bottom surface of the dielectric structure, and a second via landing on the feedthrough via. The first via and the second via have substantially coplanar bottom surfaces.

Abstract: A semiconductor structure includes a metal gate structure having a gate dielectric layer and a gate electrode. A topmost surface of the gate dielectric layer is above a topmost surface of the gate electrode. The semiconductor structure further includes a conductive layer disposed on the gate electrode of the metal gate structure, the conductive layer having a bottom portion disposed laterally between sidewalls of the gate dielectric layer and a top portion disposed above the topmost surface of the gate dielectric layer. The semiconductor structure further includes a contact feature in direct contact with the top portion of the conductive layer.

Abstract: The disclosure provides a two-dimensional photonic integrated quantum walk chip and system, including a two-dimensional photonic integrated quantum walk structure. The two-dimensional photonic integrated quantum walk structure includes a cladding and at least two waveguide layers stacked in a thickness direction, each of the waveguide layers including at least two waveguides, the cladding wrapping the waveguides; the waveguides are parallel to each other, and arranged in a matrix on a plane perpendicular to an extension direction of the waveguides; any one of the waveguides is coupled with the waveguides in a row direction, a column direction and a diagonal direction. By arranging multiple waveguide layers and arranging at least two waveguides in each waveguide layer, a waveguide array in matrix arrangement can be formed, and any waveguide is coupled with the waveguides in the row direction, the column direction and the diagonal direction.

Abstract: Semiconductor structures and methods are provided. An exemplary method according to the present disclosure includes providing a workpiece including a semiconductor fin protruding from a substrate, a first placeholder gate and a second placeholder gate over channel regions of the semiconductor fin, and a source/drain feature disposed between the channel regions. The method also includes removing a portion of the first placeholder gate and a portion of the substrate directly disposed thereunder to form an isolation trench, forming a dielectric feature in the isolation trench, replacing the second placeholder gate with a metal gate stack, selectively recessing the dielectric feature, forming a first capping layer over the metal gate stack and a second capping layer over the recessed dielectric feature, and forming a source/drain contact over and electrically coupled to the source/drain feature.

Abstract: A control valve is provided, which comprises a valve body and a valve element. The valve element can be driven to rotate, the valve element is provided with an external communicating cavity and a first cavity, and the valve element comprises a first partition plate, a first valve element shaft and a first reinforcing rib; the first reinforcing rib comprises a first end portion, a second end portion and a first main body portion in a height direction of the valve element and the first main body portion is connected between the first end portion and the second end portion, and there is a height difference between the first end portion and the second end portion.

Abstract: The present disclosure provides a method for correcting face distortion, an apparatus for correcting face distortion, an electronic device, and a storage medium. The method includes: performing face detection on an obtained image to determine a position of each face box included in the image; determining whether each face box is within a predetermined field of view range based on the position of the face box; and performing distortion correction on a face in a first face box in response to at least a part of the first face box being not within the predetermined field of view range, to generate a corrected image.

Abstract: A semiconductor structure includes a substrate, a first transistor disposed over the substrate and including a first channel, a first interfacial layer over the first channel, a first gate dielectric layer over the first interfacial layer, and a first gate electrode layer over the first gate dielectric layer, and a second transistor disposed over the substrate and including a second channel, a second interfacial layer over the second channel, a second gate dielectric layer over the second interfacial layer, and a second gate electrode layer over the second gate dielectric layer. The first gate dielectric layer includes a first dipole material composition having a first maximum concentration at a half-thickness line of the first gate dielectric layer. The second gate dielectric layer includes a second dipole material composition having a second maximum concentration at a half-thickness line of the second gate dielectric layer and greater than the first maximum concentration.

Abstract: A control valve, includes a valve body, a valve core, and a sealing component. The control valve includes communication ports; the communication ports are communicated with a valve cavity (101); the communication ports comprise first communication ports; the first communication ports are arranged along the height direction of a side wall portion and the circumferential direction of the side wall portion; two first communication ports is arranged on the side wall portion along the circumferential direction of the side wall portion; the sealing component includes a sealing body portion; the sealing body portion is located between the valve core (20) and the side wall portion; the sealing body portion has through holes.

Abstract: In an embodiment, a device includes: a gate electrode; a epitaxial source/drain region adjacent the gate electrode; one or more inter-layer dielectric (ILD) layers over the epitaxial source/drain region; a first source/drain contact extending through the ILD layers, the first source/drain contact connected to the epitaxial source/drain region; a contact spacer surrounding the first source/drain contact; and a void disposed between the contact spacer and the ILD layers.

Abstract: The application discloses an extremely low thermal conductivity direct current line forming method, including: adopting a guide wire made of a titanium alloy material, wrapping the guide wire with an insulating paint layer to form a wire, twisting the wire for multiple times to sequentially form a small wire pair, a large wire pair, a wire set and a wire core, and wrapping the wire core with an outer sheath made of a non-metallic material to form a direct current line. The application further discloses a direct current line used for a quantum computer and manufactured through the extremely low heat conductivity direct current line forming method.

Abstract: An embodiment detects by a Clustering Component of a Recommendation System, a candidate content based on a user query, responsive to the detected candidate content, executes a clustering algorithm on the detected candidate content to output a cluster and a cluster result. The embodiment decides, by a Recommendation Clarification Component of the Recommendation System, to recommend a clarification based on the cluster result, comprising computing a distance between a cluster and a response of a large language model to the user query where an option list is updated with the clarification where the clarification is based on the cluster and the distance. The embodiment also detects by the Recommendation System a selection in the option list, responsive to the detected selection, generates a prompt based on the selection where the prompt is inputted into the Recommendation System and the large language model.

Abstract: A method of operating a display includes performing a non-synchronized touch scan pattern on a display with a controller coupled to the display. The non-synchronized touch scan pattern schedules touch scans independent of a refresh rate of the display. Upon the controller detecting a first synchronization pulse from a display controller coupled to the controller and the display, a first pulse-checking timer is started. Upon detecting a second synchronization pulse from the display controller and before the first pulse-checking timer expires, a first display refresh rate for the display is obtained from an interval between the first synchronization pulse and the second synchronization pulse. A synchronized touch scan pattern is performed with the controller, and is scheduled to avoid touch scans coinciding with refreshes of the display performed at the first display refresh rate.

Abstract: Implementations of the subject matter described herein relate to generating animated infographics from static infographics. A computer-implemented method comprises: extracting visual elements of a static infographic; determining, based on the visual elements, a structure of the static infographic at least indicating a layout of the visual elements in the static infographic; and applying a dynamic effect to the visual elements based on the structure of the static infographic to generate an animated infographic.

Abstract: A method for monitoring a battery module in a vehicle includes selecting an upper cut-off voltage and a lower cut-off voltage for the battery module. The method includes charging the battery cell from an original state to a first benchmark voltage greater than an upper cut-off voltage, via a first charging process. The method includes discharging the battery cell from the first benchmark voltage to a second benchmark voltage less than a lower cut-off voltage, via a first discharging process. The battery module is then charged from the second benchmark voltage to the first benchmark voltage, via a second charging process. The method includes obtaining a ratio of a discharging capacity to a charging capacity of the battery module. Operation of the vehicle is controlled based in part on the ratio, including taking at least one remedial action if the ratio is less than a predefined threshold.

Abstract: A light emitting diode package structure includes one or more lead frame units, a light emitting element, and an encapsulation unit that completely covers the light emitting element and partially covers the lead frame units. Each lead frame unit includes a chip-mounted portion, a first electrode portion, and a second electrode portion. The first and the second electrode portion extend along a first direction, and are disposed on two sides of the chip-mounted portion. Each lead frame unit further includes multiple first connecting portions extending from the chip-mounted portion along the first direction, and multiple second connecting portions formed by extension of the first and the second electrode portion along a second direction. The light emitting element is fixed to the chip-mounted portion and electrically connected to the electrode portions. A lead frame that includes the at least one lead frame unit is also provided.

Abstract: A fistula blocking stent, a stent delivering system, and a method of delivering a fistula blocking stent are provided. The fistula blocking stent is configured to seal a fistula formed between a first lumen and a second lumen, which includes a first fixing stent in a shape of a hollow tube, the first fixing stent having a proximal end, a distal end, and a first tube extending axially between the proximal end and the distal end, the first fixing stent being provided in the first lumen; a second fixing stent provided in the fistula and the second lumen, the second fixing stent having a first end and a second end opposite to the first end, the first end being connected to the first fixing stent; and a barrier film provided on at least one of the first fixing stent and the second fixing stent and configured to seal the fistula.

Abstract: A gene editing system of Candida viswanathii includes a Candida viswanathii, a first gene editing fragment and a second gene editing fragment. The first gene editing fragment successively includes a first homology arm and a screening gene. The second gene editing fragment is connected to a C-terminus of the first gene editing fragment and includes a second homology arm, a Cas9 expression cassette and a sgRNA cassette. The Cas9 expression cassette successively includes a Cas9 promoter, a Cas9 gene and three nuclear localization sequences. The sgRNA cassette successively includes a sgRNA promoter, a first ribozyme, a targeting sequence, a scaffold and a second ribozyme. The first gene editing fragment and the second gene editing fragment are constructed as a linear fragment for gene editing of a chromosome of the Candida viswanathii.

Abstract: Epitaxial source/drain structures for enhancing performance of multigate devices, such as fin-like field-effect transistors (FETs) or gate-all-around (GAA) FETs, and methods of fabricating the epitaxial source/drain structures, are disclosed herein. An exemplary device includes a dielectric substrate. The device further includes a channel layer, a gate disposed over the channel layer, and an epitaxial source/drain structure disposed adjacent to the channel layer. The channel layer, the gate, and the epitaxial source/drain structure are disposed over the dielectric substrate. The epitaxial source/drain structure includes an inner portion having a first dopant concentration and an outer portion having a second dopant concentration that is less than the first dopant concentration. The inner portion physically contacts the dielectric substrate, and the outer portion is disposed between the inner portion and the channel layer. In some embodiments, the outer portion physically contacts the dielectric substrate.