Patents by Inventor Yun Wang

Yun Wang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20250147626
    Abstract: A method of operating a display includes performing a non-synchronized touch scan pattern on a display with a controller coupled to the display. The non-synchronized touch scan pattern schedules touch scans independent of a refresh rate of the display. Upon the controller detecting a first synchronization pulse from a display controller coupled to the controller and the display, a first pulse-checking timer is started. Upon detecting a second synchronization pulse from the display controller and before the first pulse-checking timer expires, a first display refresh rate for the display is obtained from an interval between the first synchronization pulse and the second synchronization pulse. A synchronized touch scan pattern is performed with the controller, and is scheduled to avoid touch scans coinciding with refreshes of the display performed at the first display refresh rate.
    Type: Application
    Filed: January 13, 2025
    Publication date: May 8, 2025
    Inventors: Pengcheng Wen, Yuan Yun Wang
  • Publication number: 20250148686
    Abstract: Implementations of the subject matter described herein relate to generating animated infographics from static infographics. A computer-implemented method comprises: extracting visual elements of a static infographic; determining, based on the visual elements, a structure of the static infographic at least indicating a layout of the visual elements in the static infographic; and applying a dynamic effect to the visual elements based on the structure of the static infographic to generate an animated infographic.
    Type: Application
    Filed: December 31, 2024
    Publication date: May 8, 2025
    Inventors: Yun Wang, He Huang, Haidong Zhang
  • Publication number: 20250134506
    Abstract: A fistula blocking stent, a stent delivering system, and a method of delivering a fistula blocking stent are provided. The fistula blocking stent is configured to seal a fistula formed between a first lumen and a second lumen, which includes a first fixing stent in a shape of a hollow tube, the first fixing stent having a proximal end, a distal end, and a first tube extending axially between the proximal end and the distal end, the first fixing stent being provided in the first lumen; a second fixing stent provided in the fistula and the second lumen, the second fixing stent having a first end and a second end opposite to the first end, the first end being connected to the first fixing stent; and a barrier film provided on at least one of the first fixing stent and the second fixing stent and configured to seal the fistula.
    Type: Application
    Filed: June 28, 2024
    Publication date: May 1, 2025
    Inventors: Yun Wang, Jiwang Wang, Guoxin Zhang, Weifeng Zhang, Lurong Li, Jianyu Wei, Zhenghua Shen, Changqing Li, Derong Leng
  • Publication number: 20250135946
    Abstract: A method for monitoring a battery module in a vehicle includes selecting an upper cut-off voltage and a lower cut-off voltage for the battery module. The method includes charging the battery cell from an original state to a first benchmark voltage greater than an upper cut-off voltage, via a first charging process. The method includes discharging the battery cell from the first benchmark voltage to a second benchmark voltage less than a lower cut-off voltage, via a first discharging process. The battery module is then charged from the second benchmark voltage to the first benchmark voltage, via a second charging process. The method includes obtaining a ratio of a discharging capacity to a charging capacity of the battery module. Operation of the vehicle is controlled based in part on the ratio, including taking at least one remedial action if the ratio is less than a predefined threshold.
    Type: Application
    Filed: October 25, 2023
    Publication date: May 1, 2025
    Applicant: GM GLOBAL TECHNOLOGY OPERATIONS LLC
    Inventors: Yongjie Zhu, Meng Jiang, Andrew C. Baughman, Xueyu Zhang, Chunhao J. Lee, Yue-Yun Wang
  • Publication number: 20250143046
    Abstract: A light emitting diode package structure includes one or more lead frame units, a light emitting element, and an encapsulation unit that completely covers the light emitting element and partially covers the lead frame units. Each lead frame unit includes a chip-mounted portion, a first electrode portion, and a second electrode portion. The first and the second electrode portion extend along a first direction, and are disposed on two sides of the chip-mounted portion. Each lead frame unit further includes multiple first connecting portions extending from the chip-mounted portion along the first direction, and multiple second connecting portions formed by extension of the first and the second electrode portion along a second direction. The light emitting element is fixed to the chip-mounted portion and electrically connected to the electrode portions. A lead frame that includes the at least one lead frame unit is also provided.
    Type: Application
    Filed: October 25, 2024
    Publication date: May 1, 2025
    Inventors: HSIN-HUI LIANG, CHENG-HONG SU, CHEN-HSIU LIN, CHIH-LI YU, CHENG-HAN WANG, SHENG-YUN WANG
  • Patent number: 12286663
    Abstract: A gene editing system of Candida viswanathii includes a Candida viswanathii, a first gene editing fragment and a second gene editing fragment. The first gene editing fragment successively includes a first homology arm and a screening gene. The second gene editing fragment is connected to a C-terminus of the first gene editing fragment and includes a second homology arm, a Cas9 expression cassette and a sgRNA cassette. The Cas9 expression cassette successively includes a Cas9 promoter, a Cas9 gene and three nuclear localization sequences. The sgRNA cassette successively includes a sgRNA promoter, a first ribozyme, a targeting sequence, a scaffold and a second ribozyme. The first gene editing fragment and the second gene editing fragment are constructed as a linear fragment for gene editing of a chromosome of the Candida viswanathii.
    Type: Grant
    Filed: March 24, 2023
    Date of Patent: April 29, 2025
    Assignees: NATIONAL TSING HUA UNIVERSITY, Chang Chun Plastics Co., Ltd., Chang Chun Petrochemical Co., LTD., DAIREN CHEMICAL CORP.
    Inventors: Yu-Chen Hu, Nam Ngoc Pham, June-Yen Chou, Hsing-Yun Wang, Vincent Jianan Liu
  • Patent number: 12283630
    Abstract: Epitaxial source/drain structures for enhancing performance of multigate devices, such as fin-like field-effect transistors (FETs) or gate-all-around (GAA) FETs, and methods of fabricating the epitaxial source/drain structures, are disclosed herein. An exemplary device includes a dielectric substrate. The device further includes a channel layer, a gate disposed over the channel layer, and an epitaxial source/drain structure disposed adjacent to the channel layer. The channel layer, the gate, and the epitaxial source/drain structure are disposed over the dielectric substrate. The epitaxial source/drain structure includes an inner portion having a first dopant concentration and an outer portion having a second dopant concentration that is less than the first dopant concentration. The inner portion physically contacts the dielectric substrate, and the outer portion is disposed between the inner portion and the channel layer. In some embodiments, the outer portion physically contacts the dielectric substrate.
    Type: Grant
    Filed: November 29, 2023
    Date of Patent: April 22, 2025
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Chen-Ming Lee, I-Wen Wu, Po-Yu Huang, Fu-Kai Yang, Mei-Yun Wang
  • Patent number: 12282069
    Abstract: Systems and methods for diagnosing health of a battery using in-vehicle impedance analysis. The method includes receiving a sensed current measurement for a cell of the battery; generating a current profile as a function of the sensed current measurement, including pulses to a peak current, the pulses having a pulse frequency (w); applying a current with the current profile to the cell; for each pulse in the current profile, receiving a voltage measurement for the cell that is responsive to the pulse, calculating an impedance for the cell responsive thereto, the impedance comprising a real component at the pulse frequency (RZw), and an imaginary component at the pulse frequency (IZw), identifying a battery health problem when either RZw exceeds a preprogrammed first threshold for the pulse frequency, or when IZw exceeds a preprogrammed second threshold for the pulse frequency, and storing the RZw and the IZw for the cell.
    Type: Grant
    Filed: January 13, 2022
    Date of Patent: April 22, 2025
    Assignee: GM GLOBAL TECHNOLOGY OPERATIONS LLC
    Inventors: Yue-Yun Wang, Steven Earl Muldoon, Lei Hao, Michael P Barker
  • Patent number: 12278188
    Abstract: Vias, along with methods for fabricating vias, are disclosed that exhibit reduced capacitance and resistance. An exemplary interconnect structure includes a first source/drain contact and a second source/drain contact disposed in a dielectric layer. The first source/drain contact physically contacts a first source/drain feature and the second source/drain contact physically contacts a second source/drain feature. A first via having a first via layer configuration, a second via having a second via layer configuration, and a third via having a third via layer configuration are disposed in the dielectric layer. The first via and the second via extend into and physically contact the first source/drain contact and the second source/drain contact, respectively. A first thickness of the first via and a second thickness of the second via are the same. The third via physically contacts a gate structure, which is disposed between the first source/drain contact and the second source/drain contact.
    Type: Grant
    Filed: June 30, 2023
    Date of Patent: April 15, 2025
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Shih-Che Lin, Po-Yu Huang, Chao-Hsun Wang, Kuo-Yi Chao, Mei-Yun Wang, Feng-Yu Chang, Rueijer Lin, Wei-Jung Lin, Chen-Yuan Kao
  • Publication number: 20250120122
    Abstract: One aspect of the present disclosure pertains to a semiconductor device. The semiconductor device includes a semiconductor substrate and a transistor formed over the semiconductor substrate. The transistor includes a first source/drain (S/D) feature, a second S/D feature, a channel region interposed between the first and second S/D features, and a gate stack engaging the channel region. The semiconductor device includes a first S/D contact landing on a top surface of the first S/D feature, a second S/D contact landing on a top surface of the second S/D feature, and a dielectric plug penetrating through the semiconductor substrate and landing on a bottom surface of the first S/D feature. The dielectric plug spans a width equal to or smaller than a width of the first S/D feature.
    Type: Application
    Filed: October 5, 2023
    Publication date: April 10, 2025
    Inventors: Chen-Ming Lee, Shih-Chieh Wu, Po-Yu Huang, I-Wen Wu, Fu-Kai Yang, Mei-Yun Wang
  • Publication number: 20250111650
    Abstract: A deep learning method of an artificial intelligence model for medical image recognition is provided. The method includes the following steps: obtaining a first image set, where the first image set includes at least two images captured with different parameters; performing image pre-processing on each image of the first image set to obtain a second image set; performing image augmentation on the second image set to obtain a third image set; adding the third image set to a training image data set; and training the artificial intelligence model using the training image data set.
    Type: Application
    Filed: February 15, 2024
    Publication date: April 3, 2025
    Inventors: Chia-Yuan CHANG, Chen-Hwa SUNG, Gigin LIN, Tzu-Hsiang YANG, Tzu-Yun WANG, Chien-Yu HUANG
  • Patent number: 12267048
    Abstract: A common-emitter amplifier with unilateral pre-embedding inductors includes: an input matching circuit, a first-stage amplification circuit, a first-stage interstage matching circuit, a second-stage amplification circuit, a second-stage interstage matching circuit, a third-stage amplification circuit, and an output matching circuit. The common-emitter amplifier is configured to: make an input signal sequentially enter bases of common-emitter transistors of the first-stage, second-stage, and third-stage amplification circuits, make the input signal be amplified stage by stage by the common-emitter transistors, and finally make an amplified input signal obtained by amplifying of each common-emitter transistor output through a collector of each common-emitter transistor. The common-emitter amplifier is configured to introduce interstage staggered tuning to expand bandwidth to address a narrowband problem.
    Type: Grant
    Filed: December 9, 2024
    Date of Patent: April 1, 2025
    Assignee: Beijing University of Posts and Telecommunications
    Inventors: Jianguo Yu, Xiaorui Liu, Yun Wang, Kaile Li, Yibo Huang, Feixiang Zhang, Zhihe Wu
  • Patent number: 12264106
    Abstract: A cerium-zirconium-aluminum-based composite material, a cGPF catalyst and a preparation method thereof are provided. The cerium-zirconium-aluminum-based composite material adopts a stepwise precipitation method, firstly preparing an aluminum-based pre-treated material, then coprecipitating the aluminum-based pre-treated material with zirconium and cerium sol, and finally roasting at high temperature to obtain the cerium-zirconium-aluminum-based composite material. The cerium-zirconium-aluminum-based composite material has better compactness and higher density, and when it is used in cGPF catalyst, it occupies a smaller volume of pores on the catalyst carrier, such that cGPF catalyst has lower back pressure and better ash accumulation resistance, which is beneficial to large-scale application of cGPF catalyst.
    Type: Grant
    Filed: June 17, 2020
    Date of Patent: April 1, 2025
    Assignee: SINOTECH COMPANY LIMITED
    Inventors: Dacheng Li, Jinfeng Wang, Li Lan, Hui Ye, Lan Yang, Feng Zhang, Yi Yang, Yongxiang Cheng, Tiantian Luo, Yinhua Dong, Yun Wang, Yun Li, Qizhang Chen
  • Patent number: 12266606
    Abstract: Semiconductor device and the manufacturing method thereof are disclosed. An exemplary semiconductor device comprises a dielectric layer formed over a power rail; a bottom semiconductor layer formed over the dielectric layer; a backside spacer formed along a sidewall of the bottom semiconductor layer; a conductive feature contacting a sidewall of the dielectric layer and a sidewall of the backside spacer; channel semiconductor layers over the bottom semiconductor layer, wherein the channel semiconductor layers are stacked up and separated from each other; a metal gate structure wrapping each of the channel semiconductor layers; and an epitaxial source/drain (S/D) feature contacting a sidewall of each of the channel semiconductor layers, wherein the epitaxial S/D feature contacts the conductive feature, and the conductive feature contacts the power rail.
    Type: Grant
    Filed: July 20, 2023
    Date of Patent: April 1, 2025
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Po-Yu Huang, Chia-Hsien Yao, Fu-Kai Yang, Mei-Yun Wang
  • Patent number: 12266703
    Abstract: An interconnect fabrication method is disclosed herein that utilizes a disposable etch stop hard mask over a gate structure during source/drain contact formation and replaces the disposable etch stop hard mask with a dielectric feature (in some embodiments, dielectric layers having a lower dielectric constant than a dielectric constant of dielectric layers of the disposable etch stop hard mask) before gate contact formation. An exemplary device includes a contact etch stop layer (CESL) having a first sidewall CESL portion and a second sidewall CESL portion separated by a spacing and a dielectric feature disposed over a gate structure, where the dielectric feature and the gate structure fill the spacing between the first sidewall CESL portion and the second sidewall CESL portion. The dielectric feature includes a bulk dielectric over a dielectric liner. The dielectric liner separates the bulk dielectric from the gate structure and the CESL.
    Type: Grant
    Filed: December 9, 2021
    Date of Patent: April 1, 2025
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Shih-Che Lin, Po-Yu Huang, I-Wen Wu, Chen-Ming Lee, Chia-Hsien Yao, Chao-Hsun Wang, Fu-Kai Yang, Mei-Yun Wang
  • Publication number: 20250102585
    Abstract: A system for estimating a state-of-charge of a battery assembly includes a sensor cell and an estimator circuit. The sensor cell is coupled in series to the battery assembly. The battery assembly has an assembly battery chemistry and the sensor cell has a sensor battery chemistry, and the assembly battery chemistry is different than the sensor battery chemistry. The estimator circuit is operational to acquire a sequence of current sensor cell state-of-charges based on a sensor cell model and a sequence of sensor voltages across the sensor cell, calculate a sequence of current battery assembly state-of-charges based on the sequence of current sensor cell state-of-charges, and calculate an estimated battery assembly state-of-charge of the battery assembly and an estimated sensor cell state-of-charge of the sensor cell by filtering in parallel the sequence of current battery assembly state-of-charges and the sequence of current sensor cell state-of-charges.
    Type: Application
    Filed: September 27, 2023
    Publication date: March 27, 2025
    Applicant: GM GLOBAL TECHNOLOGY OPERATIONS LLC
    Inventors: Yue-Yun Wang, Charles W. Wampler, Chen-Fang Chang
  • Publication number: 20250099936
    Abstract: Disclosed are emulsion gel with both a freshness indication and a low migration rate, and a preparation method therefor. Lipase and organic acid are used and subjected to hydrophobic modification of anthocyanins to obtain acylated anthocyanins, the acylated anthocyanins and oil-phase gel are then dissolved in vegetable oil to form an oil phase, while a sodium alginate aqueous solution is used as a water phase, the oil phase and the water phase are mixed and subjected to high-speed shearing, and calcium carbonate and glucono-?-lactone are finally added for high-speed shearing to form emulsion gel. The emulsion gel prepared in the present disclosure has both a freshness indication and a low migration rate, and the preparation method of the present disclosure is simple, green, pollution-free and low energy consumption.
    Type: Application
    Filed: December 9, 2024
    Publication date: March 27, 2025
    Inventors: Long CHEN, Jiaqi Zhong, Hao Cheng, Kuang He, Ziqiang Lin, Zhengyu Jin, Yun Wang, Liyi Chen, Huichang Zhong, Yaoqi Tian, Jianwei Zhao, Xing Zhou, Jie Long, Chao Qiu, Yidong Zou, Guangxiong Chen
  • Publication number: 20250107196
    Abstract: A method according to the present disclosure includes receiving a workpiece that includes a gate structure, a first gate spacer feature, a second gate spacer feature, a gate-top dielectric feature over the gate structure, the first gate spacer feature and the second gate spacer feature, a first source/drain feature over a first source/drain region, a second source/drain feature over a second source/drain region, a first dielectric layer over the first source/drain feature, and a second dielectric layer over the second source/drain feature. The method further includes replacing a top portion of the first dielectric layer with a first hard mask layer, forming a second hard mask layer over the first hard mask layer while the second dielectric layer is exposed, etching the second dielectric layer to form a source/drain contact opening and to expose the second source/drain feature, and forming a source/drain contact over the second source/drain feature.
    Type: Application
    Filed: December 9, 2024
    Publication date: March 27, 2025
    Inventors: Ting Fang, Chia-Hsien Yao, Jui-Ping Lin, Chen-Ming Lee, Chung-Hao Cai, Fu-Kai Yang, Mei-Yun Wang
  • Publication number: 20250098300
    Abstract: A display device includes a substrate, an insulating layer and a metal layer. The substrate includes a light transmitting region. The insulating layer is disposed on the substrate and between the substrate and the metal layer. An edge of the insulating layer has a concave corner, and the concave corner is recessed toward the metal layer and located in the light transmitting region. A manufacturing method of the display device is also proposed.
    Type: Application
    Filed: December 28, 2023
    Publication date: March 20, 2025
    Inventors: HSIN-HUA TSAI, Pei-Yun WANG
  • Patent number: 12255367
    Abstract: Disclosed here is a supported catalyst comprising a thermally stable core, wherein the thermally stable core comprises a metal oxide support and nickel disposed in the metal oxide support, wherein the metal oxide support comprises at least one base metal oxide and at least one transition metal oxide or rare earth metal oxide mixed with or dispersed in the base metal oxide. Optionally the supported catalyst can further comprise an electrolyte removing layer coating the thermally stable core and/or an electrolyte repelling layer coating the electrolyte removing layer, wherein the electrolyte removing layer comprises at least one metal oxide, and wherein the electrolyte repelling layer comprises at least one of graphite, metal carbide and metal nitride. Also disclosed is a molten carbonate fuel cell comprising the supported catalyst as a direct internal reforming catalyst.
    Type: Grant
    Filed: February 10, 2023
    Date of Patent: March 18, 2025
    Assignee: FuelCell Energy, Inc.
    Inventors: Jin-Yun Wang, Mohammad Farooque, Ramakrishnan Venkataraman, Chao-Yi Yuh, April Corpuz