Abstract: A control valve, includes a valve body, a valve core, and a sealing component. The control valve includes communication ports; the communication ports are communicated with a valve cavity (101); the communication ports comprise first communication ports; the first communication ports are arranged along the height direction of a side wall portion and the circumferential direction of the side wall portion; two first communication ports is arranged on the side wall portion along the circumferential direction of the side wall portion; the sealing component includes a sealing body portion; the sealing body portion is located between the valve core (20) and the side wall portion; the sealing body portion has through holes.

Abstract: In an embodiment, a device includes: a gate electrode; a epitaxial source/drain region adjacent the gate electrode; one or more inter-layer dielectric (ILD) layers over the epitaxial source/drain region; a first source/drain contact extending through the ILD layers, the first source/drain contact connected to the epitaxial source/drain region; a contact spacer surrounding the first source/drain contact; and a void disposed between the contact spacer and the ILD layers.

Abstract: The application discloses an extremely low thermal conductivity direct current line forming method, including: adopting a guide wire made of a titanium alloy material, wrapping the guide wire with an insulating paint layer to form a wire, twisting the wire for multiple times to sequentially form a small wire pair, a large wire pair, a wire set and a wire core, and wrapping the wire core with an outer sheath made of a non-metallic material to form a direct current line. The application further discloses a direct current line used for a quantum computer and manufactured through the extremely low heat conductivity direct current line forming method.

Abstract: An embodiment detects by a Clustering Component of a Recommendation System, a candidate content based on a user query, responsive to the detected candidate content, executes a clustering algorithm on the detected candidate content to output a cluster and a cluster result. The embodiment decides, by a Recommendation Clarification Component of the Recommendation System, to recommend a clarification based on the cluster result, comprising computing a distance between a cluster and a response of a large language model to the user query where an option list is updated with the clarification where the clarification is based on the cluster and the distance. The embodiment also detects by the Recommendation System a selection in the option list, responsive to the detected selection, generates a prompt based on the selection where the prompt is inputted into the Recommendation System and the large language model.

Abstract: An illumination system includes a micro-LED array having a plurality of individually addressable diodes, a concentrator array overlying an output of the micro-LED array and configured to decrease a numerical aperture of light emitted by the array, and a non-emissive display panel arranged to receive light from the concentrator array.

Abstract: A control valve is provided, which comprises a valve body, a valve core, a sealing component and a balance sealing block. The control valve comprises at least five channels. A side wall part is provided with at least five communication ports. The communication ports are in communication with a valve cavity. A sealing body part of the sealing component is positioned between the valve core and the side wall part. The sealing body part is provided with through holes penetrating through the sealing component. In the region of the side wall part that in contact with the sealing body part, the number of communication ports is the same as the number of through holes, and the communication ports and the through holes are in communication correspondingly.

Abstract: A method of operating a display includes performing a non-synchronized touch scan pattern on a display with a controller coupled to the display. The non-synchronized touch scan pattern schedules touch scans independent of a refresh rate of the display. Upon the controller detecting a first synchronization pulse from a display controller coupled to the controller and the display, a first pulse-checking timer is started. Upon detecting a second synchronization pulse from the display controller and before the first pulse-checking timer expires, a first display refresh rate for the display is obtained from an interval between the first synchronization pulse and the second synchronization pulse. A synchronized touch scan pattern is performed with the controller, and is scheduled to avoid touch scans coinciding with refreshes of the display performed at the first display refresh rate.

Abstract: Implementations of the subject matter described herein relate to generating animated infographics from static infographics. A computer-implemented method comprises: extracting visual elements of a static infographic; determining, based on the visual elements, a structure of the static infographic at least indicating a layout of the visual elements in the static infographic; and applying a dynamic effect to the visual elements based on the structure of the static infographic to generate an animated infographic.

Abstract: A method for monitoring a battery module in a vehicle includes selecting an upper cut-off voltage and a lower cut-off voltage for the battery module. The method includes charging the battery cell from an original state to a first benchmark voltage greater than an upper cut-off voltage, via a first charging process. The method includes discharging the battery cell from the first benchmark voltage to a second benchmark voltage less than a lower cut-off voltage, via a first discharging process. The battery module is then charged from the second benchmark voltage to the first benchmark voltage, via a second charging process. The method includes obtaining a ratio of a discharging capacity to a charging capacity of the battery module. Operation of the vehicle is controlled based in part on the ratio, including taking at least one remedial action if the ratio is less than a predefined threshold.

Abstract: A light emitting diode package structure includes one or more lead frame units, a light emitting element, and an encapsulation unit that completely covers the light emitting element and partially covers the lead frame units. Each lead frame unit includes a chip-mounted portion, a first electrode portion, and a second electrode portion. The first and the second electrode portion extend along a first direction, and are disposed on two sides of the chip-mounted portion. Each lead frame unit further includes multiple first connecting portions extending from the chip-mounted portion along the first direction, and multiple second connecting portions formed by extension of the first and the second electrode portion along a second direction. The light emitting element is fixed to the chip-mounted portion and electrically connected to the electrode portions. A lead frame that includes the at least one lead frame unit is also provided.

Abstract: A fistula blocking stent, a stent delivering system, and a method of delivering a fistula blocking stent are provided. The fistula blocking stent is configured to seal a fistula formed between a first lumen and a second lumen, which includes a first fixing stent in a shape of a hollow tube, the first fixing stent having a proximal end, a distal end, and a first tube extending axially between the proximal end and the distal end, the first fixing stent being provided in the first lumen; a second fixing stent provided in the fistula and the second lumen, the second fixing stent having a first end and a second end opposite to the first end, the first end being connected to the first fixing stent; and a barrier film provided on at least one of the first fixing stent and the second fixing stent and configured to seal the fistula.

Abstract: A gene editing system of Candida viswanathii includes a Candida viswanathii, a first gene editing fragment and a second gene editing fragment. The first gene editing fragment successively includes a first homology arm and a screening gene. The second gene editing fragment is connected to a C-terminus of the first gene editing fragment and includes a second homology arm, a Cas9 expression cassette and a sgRNA cassette. The Cas9 expression cassette successively includes a Cas9 promoter, a Cas9 gene and three nuclear localization sequences. The sgRNA cassette successively includes a sgRNA promoter, a first ribozyme, a targeting sequence, a scaffold and a second ribozyme. The first gene editing fragment and the second gene editing fragment are constructed as a linear fragment for gene editing of a chromosome of the Candida viswanathii.

Abstract: Epitaxial source/drain structures for enhancing performance of multigate devices, such as fin-like field-effect transistors (FETs) or gate-all-around (GAA) FETs, and methods of fabricating the epitaxial source/drain structures, are disclosed herein. An exemplary device includes a dielectric substrate. The device further includes a channel layer, a gate disposed over the channel layer, and an epitaxial source/drain structure disposed adjacent to the channel layer. The channel layer, the gate, and the epitaxial source/drain structure are disposed over the dielectric substrate. The epitaxial source/drain structure includes an inner portion having a first dopant concentration and an outer portion having a second dopant concentration that is less than the first dopant concentration. The inner portion physically contacts the dielectric substrate, and the outer portion is disposed between the inner portion and the channel layer. In some embodiments, the outer portion physically contacts the dielectric substrate.

Abstract: Systems and methods for diagnosing health of a battery using in-vehicle impedance analysis. The method includes receiving a sensed current measurement for a cell of the battery; generating a current profile as a function of the sensed current measurement, including pulses to a peak current, the pulses having a pulse frequency (w); applying a current with the current profile to the cell; for each pulse in the current profile, receiving a voltage measurement for the cell that is responsive to the pulse, calculating an impedance for the cell responsive thereto, the impedance comprising a real component at the pulse frequency (RZw), and an imaginary component at the pulse frequency (IZw), identifying a battery health problem when either RZw exceeds a preprogrammed first threshold for the pulse frequency, or when IZw exceeds a preprogrammed second threshold for the pulse frequency, and storing the RZw and the IZw for the cell.

Abstract: Vias, along with methods for fabricating vias, are disclosed that exhibit reduced capacitance and resistance. An exemplary interconnect structure includes a first source/drain contact and a second source/drain contact disposed in a dielectric layer. The first source/drain contact physically contacts a first source/drain feature and the second source/drain contact physically contacts a second source/drain feature. A first via having a first via layer configuration, a second via having a second via layer configuration, and a third via having a third via layer configuration are disposed in the dielectric layer. The first via and the second via extend into and physically contact the first source/drain contact and the second source/drain contact, respectively. A first thickness of the first via and a second thickness of the second via are the same. The third via physically contacts a gate structure, which is disposed between the first source/drain contact and the second source/drain contact.

Abstract: One aspect of the present disclosure pertains to a semiconductor device. The semiconductor device includes a semiconductor substrate and a transistor formed over the semiconductor substrate. The transistor includes a first source/drain (S/D) feature, a second S/D feature, a channel region interposed between the first and second S/D features, and a gate stack engaging the channel region. The semiconductor device includes a first S/D contact landing on a top surface of the first S/D feature, a second S/D contact landing on a top surface of the second S/D feature, and a dielectric plug penetrating through the semiconductor substrate and landing on a bottom surface of the first S/D feature. The dielectric plug spans a width equal to or smaller than a width of the first S/D feature.

Abstract: A deep learning method of an artificial intelligence model for medical image recognition is provided. The method includes the following steps: obtaining a first image set, where the first image set includes at least two images captured with different parameters; performing image pre-processing on each image of the first image set to obtain a second image set; performing image augmentation on the second image set to obtain a third image set; adding the third image set to a training image data set; and training the artificial intelligence model using the training image data set.

Abstract: An interconnect fabrication method is disclosed herein that utilizes a disposable etch stop hard mask over a gate structure during source/drain contact formation and replaces the disposable etch stop hard mask with a dielectric feature (in some embodiments, dielectric layers having a lower dielectric constant than a dielectric constant of dielectric layers of the disposable etch stop hard mask) before gate contact formation. An exemplary device includes a contact etch stop layer (CESL) having a first sidewall CESL portion and a second sidewall CESL portion separated by a spacing and a dielectric feature disposed over a gate structure, where the dielectric feature and the gate structure fill the spacing between the first sidewall CESL portion and the second sidewall CESL portion. The dielectric feature includes a bulk dielectric over a dielectric liner. The dielectric liner separates the bulk dielectric from the gate structure and the CESL.

Abstract: A cerium-zirconium-aluminum-based composite material, a cGPF catalyst and a preparation method thereof are provided. The cerium-zirconium-aluminum-based composite material adopts a stepwise precipitation method, firstly preparing an aluminum-based pre-treated material, then coprecipitating the aluminum-based pre-treated material with zirconium and cerium sol, and finally roasting at high temperature to obtain the cerium-zirconium-aluminum-based composite material. The cerium-zirconium-aluminum-based composite material has better compactness and higher density, and when it is used in cGPF catalyst, it occupies a smaller volume of pores on the catalyst carrier, such that cGPF catalyst has lower back pressure and better ash accumulation resistance, which is beneficial to large-scale application of cGPF catalyst.

Abstract: Semiconductor device and the manufacturing method thereof are disclosed. An exemplary semiconductor device comprises a dielectric layer formed over a power rail; a bottom semiconductor layer formed over the dielectric layer; a backside spacer formed along a sidewall of the bottom semiconductor layer; a conductive feature contacting a sidewall of the dielectric layer and a sidewall of the backside spacer; channel semiconductor layers over the bottom semiconductor layer, wherein the channel semiconductor layers are stacked up and separated from each other; a metal gate structure wrapping each of the channel semiconductor layers; and an epitaxial source/drain (S/D) feature contacting a sidewall of each of the channel semiconductor layers, wherein the epitaxial S/D feature contacts the conductive feature, and the conductive feature contacts the power rail.