Abstract: A lighting apparatus includes a LED module, a light source plate, a heat sink, an antenna, a driver and a light housing. The light source plate is used for holding the LED module. The heat sink has a bottom plate and a lateral wall. The light source plate is placed on the bottom plate. The antenna is disposed on the lateral wall. The driver is used for generating a driving current to the LED module. The driver has a wireless circuit. The wireless circuit is electrically connected to the antenna for transmitting a wireless signal. The light housing is used for holding the heat sink so that the LED module emits light toward a light opening of the light housing.

Abstract: A device includes a gate stack; a gate spacer on a sidewall of the gate stack; a source/drain region adjacent the gate stack; a silicide; and a source/drain contact electrically connected to the source/drain region through the silicide. The silicide includes a conformal first portion in the source/drain region, the conformal first portion comprising a metal and silicon; and a conformal second portion over the conformal first portion, the conformal second portion further disposed on a sidewall of the gate spacer, the conformal second portion comprising the metal, silicon, and nitrogen.

Abstract: Methods and devices including an air gap adjacent a contact element extending to a source/drain feature of a device are described. Some embodiments of the method include depositing a dummy layer, which is subsequently removed to form the air gap. The dummy layer and subsequent air gap may be formed after a SAC dielectric layer such as silicon nitride is formed over an adjacent metal gate structure.

Abstract: To reduce the amount of space occupied in the inactive area of a display by gate driver circuitry, at least a portion of the gate driver circuitry may be positioned in the active area of the display. To accommodate the gate driver circuitry, emissive sub-pixels may be laterally shifted relative to corresponding thin-film transistor sub-pixels. This allows for the thin-film transistor sub-pixels to be grouped adjacent to the central area of the active area, leaving room along an edge of the active area to accommodate one or more additional display components such as gate driver circuitry or fanout portions of data lines.

Abstract: Vertical interconnect structures and methods of forming are provided. The vertical interconnect structures may be formed by partially filling a first opening through one or more dielectric layers with layers of conductive materials. A second opening is formed in a dielectric layer such that a depth of the first opening after partially filling with the layers of conductive materials is close to a depth of the second opening. The remaining portion of the first opening and the second opening may then be simultaneously filled.

Abstract: An integrated circuit structure in which a gate overlies channel region in an active area of a first transistor. The first transistor includes a channel region, a source region and a drain region. A conductive contact is coupled to the drain region of the first transistor. A second transistor that includes a channel region, a source region a drain region is adjacent to the first transistor. The gate of the second transistor is spaced from the gate of the first transistor. A conductive via passes through an insulation layer to electrically connect to the gate of the second transistor. An expanded conductive via overlays both the conductive contact and the conductive via to electrically connect the drain of the first transistor to the gate of the second transistor.

Abstract: A method for calibrating the alignment of a wafer is provided. A plurality of alignment position deviation (APD) simulation results are obtained form a plurality of mark profiles. An alignment analysis is performed on a mark region of the wafer with a light beam. A measured APD of the mark region of the wafer is obtained in response to the light beam. The measured APD is compared with the APD simulation results to obtain alignment calibration data. An exposure process is performed on the wafer with a mask according to the alignment calibration data.

Abstract: An intelligent medical resource sharing platform is provided. The intelligent medical resource sharing platform includes a server, at least one user end device, at least one physician end device, and a consultation platform. The server includes a physiological value database, a personal record database, and a physiological value processing module. The physiological value processing module is correspondingly coupled to the physiological value database and the personal record database, and processes physiological data transmitted from the physiological value database and the personal record database.

Abstract: Embodiments of this application provide a method and an apparatus for service processing in a terminal device. The terminal device is provided with a first card and a second card. When the terminal device is using the second card for performing a voice service, if the terminal device receives a data service request that requires the first card for implementation, the terminal device may search for a cell corresponding to a first band. The cell corresponding to the first band is a cell accessed by the first card before the first card enters an idle state. Therefore, when the terminal device has found the cell corresponding to the first band, the voice service of the terminal device is not interrupted. The terminal device can implement both the data service of the first card and the voice service of the second card, allowing more usage scenarios for the terminal device.

Abstract: A method and apparatus for electric motor control includes a model predictive controller operating in a d-q reference frame to provide d-q reference frame voltage command signals that counteract a magnetic cross coupling within the motor.

Abstract: A method and apparatus for electric motor control includes a model predictive controller operating in a d-q reference frame to provide d-q reference frame voltage command signals that counteract a magnetic cross coupling within the motor.

Abstract: A terminal determines a first band of a primary card and a second band of-a secondary card; if the secondary card does not support the first band, determines a first identifier and a second identifier of a first 2R path and a third identifier and a fourth identifier of a second 2R path based on the second band, and determines a fifth identifier and a sixth identifier of a third 2R path based on the first band, where the first identifier, the third identifier, and the fifth identifier are identifiers of primary receive paths, and the second identifier, the fourth identifier, and the sixth identifier are identifiers of diversity receive paths; and determines, based on those identifiers, and a selection condition stored in the terminal, to communicate with the second base station through the secondary card by using the first 2R path or the second 2R path.

Abstract: The present disclosure provides semiconductor devices and methods of forming the same. A semiconductor device according to one embodiment of the present disclosure includes a first fin-shaped structure extending lengthwise along a first direction over a substrate, a first epitaxial feature over a source/drain region of the first fin-shaped structure, a gate structure disposed over a channel region of the first fin-shaped structure and extending along a second direction perpendicular to the first direction, and a source/drain contact over the first epitaxial feature. The bottom surface of the gate structure is closer to the substrate than a bottom surface of the source/drain contact.

Abstract: Semiconductor devices and methods of fabricating semiconductor devices are provided. The present disclosure provides a semiconductor device that includes a first fin structure and a second fin structure each extending from a substrate; a first gate segment over the first fin structure and a second gate segment over the second fin structure; a first isolation feature separating the first and second gate segments; a first source/drain (S/D) feature over the first fin structure and adjacent to the first gate segment; a second S/D feature over the second fin structure and adjacent to the second gate segment; and a second isolation feature also disposed in the trench. The first and second S/D features are separated by the second isolation feature, and a composition of the second isolation feature is different from a composition of the first isolation feature.

Abstract: Semiconductor devices and methods are provided. An exemplary method according to the present disclosure includes providing a workpiece having a channel region, a gate structure over the channel region, gate spacers extending along sidewalls of the gate structure, and an etch stop layer extending along sidewalls of the gate spacers. The method also includes performing an etching process to recess the gate spacers and the gate structure, thereby forming a funnel-shaped trench, depositing a dielectric layer over the workpiece to partially fill the funnel-shaped trench, etching back the dielectric layer to form dielectric spacers on the recessed gate spacers, forming a metal cap on the gate structure without forming the metal cap on the recessed gate spacers, and forming a dielectric cap on the metal cap.

Abstract: A semiconductor structure and a method of forming the same are provided. In an embodiment, an exemplary semiconductor structure includes a gate structure disposed over a channel region of an active region, a drain feature disposed over a drain region of the active region; a source feature disposed over a source region of the active region, a backside source contact disposed under the source feature, an isolation feature disposed on and in contact with the source feature, a drain contact disposed over and electrically coupled to the drain feature, and a gate contact via disposed over and electrically coupled to the gate structure. A distance between the gate contact via and the drain contact is greater than a distance between the gate contact via and the isolation feature. The exemplary semiconductor structure would have a reduced parasitic capacitance and an enlarged leakage window.

Abstract: A method of semiconductor fabrication includes providing a semiconductor structure having a substrate and first, second, third, and fourth fins above the substrate. The method further includes forming an n-type epitaxial source/drain (S/D) feature on the first and second fins, forming a p-type epitaxial S/D feature on the third and fourth fins, and performing a selective etch process on the semiconductor structure to remove upper portions of the n-type epitaxial S/D feature and the p-type epitaxial S/D feature such that more is removed from the n-type epitaxial S/D feature than the p-type epitaxial S/D feature.

Abstract: Semiconductor structures and methods are provided. An exemplary method according to the present disclosure includes providing a workpiece including a semiconductor fin protruding from a substrate, a first placeholder gate and a second placeholder gate over channel regions of the semiconductor fin, and a source/drain feature disposed between the channel regions. The method also includes removing a portion of the first placeholder gate and a portion of the substrate directly disposed thereunder to form an isolation trench, forming a dielectric feature in the isolation trench, replacing the second placeholder gate with a metal gate stack, selectively recessing the dielectric feature, forming a first capping layer over the metal gate stack and a second capping layer over the recessed dielectric feature, and forming a source/drain contact over and electrically coupled to the source/drain feature.

Abstract: An example operation may include one or more of identifying a newly proposed transaction of a blockchain, initiating a consensus operation to determine whether to authorize the newly proposed transaction, retrieving a key-value pair identified from a previous transaction, comparing an index value associated with the key-value pair of the previous transaction to an index value associated with a key-value pair of the newly proposed transaction, and providing an affirmative consensus to accept the newly proposed transaction in the blockchain when the index value associated with the key-value pair of the previous transaction is contiguously sequential with the index value associated with the key-value pair of the newly proposed transaction.

Abstract: Examples of an integrated circuit with an interconnect structure and a method for forming the integrated circuit are provided herein. In some examples, the method includes receiving a workpiece that includes an inter-level dielectric layer. A first contact that includes a fill material is formed that extends through the inter-level dielectric layer. The inter-level dielectric layer is recessed such that the fill material extends above a top surface of the inter-level dielectric layer. An etch-stop layer is formed on the inter-level dielectric layer such that the fill material of the first contact extends into the etch-stop layer. A second contact is formed extending through the etch-stop layer to couple to the first contact. In some such examples, the second contact physically contacts a top surface and a side surface of the first contact.