Abstract: A motor drive system of a vehicle includes: an inverter that receives power from a power source via a bus, where the inverter is connected to a motor of the vehicle; a driver that drives the inverter; a filter that filters a current signal received from the bus to generate a filtered signal; and a control module that operates in an impedance determination mode. The impedance determination mode includes: based on the filtered signal, controlling the driver and the inverter to generate a pulsed signal applied to the power source; determining a current level and a voltage of the power source due to generation of the pulsed signal, and determining impedance based on the current level and the voltage. The control modules are configured to: determine a characterization parameter of the power source based on the impedance; and perform a control operation or a countermeasure based on the characterization parameter.

Abstract: The present disclosure provides semiconductor devices and methods of forming the same. A semiconductor device according to one embodiment of the present disclosure includes a first fin-shaped structure extending lengthwise along a first direction over a substrate, a first epitaxial feature over a source/drain region of the first fin-shaped structure, a gate structure disposed over a channel region of the first fin-shaped structure and extending along a second direction perpendicular to the first direction, and a source/drain contact over the first epitaxial feature. The bottom surface of the gate structure is closer to the substrate than a bottom surface of the source/drain contact.

Abstract: The present disclosure relates to a method of analyzing a sample comprising a hydrophobic molecule. The method includes preparing an aqueous solution comprising the sample. The method also includes placing the solution in contact with a polypropylene substrate having a deactivated surface that reduces adsorption of the hydrophobic molecule relative to a polypropylene substrate that has not been deactivated. The method also includes analyzing the sample.

Abstract: According to some examples, a display system may include control circuitry, power supply circuitry, and a pixel array. Each pixel in the pixel array may include a data shift register to receive gray level data for the pixel in series and to output the gray level data in parallel. Each pixel may also include a plurality of comparators, each comparator of the plurality of comparators to receive one bit of data from the data shift register and one bit of clock data, and a NOR gates sum circuit to provide a binary output based on outputs of all of the plurality of comparators. Each pixel may further include a flip flop circuit to provide a binary output based on the binary output of the NOR gates sum circuit, and an emissions circuit to emit light at a selected gray level based on the binary output of the flip flop circuit.

Abstract: A FinFET device structure and method for forming the same is provided. The FinFET device structure includes an isolation structure formed over a substrate, and a gate structure formed over the isolation structure. The FinFET device structure includes a first dielectric layer formed over the isolation structure and adjacent to the gate structure and a source/drain (S/D) contact structure formed in the first dielectric layer. The FinFET device structure also includes a deep contact structure formed through the first dielectric layer and adjacent to the S/D contact structure. The deep contact structure is through the isolation structure, and a bottom surface of the S/D contact structure is higher than a bottom surface of the deep contact structure.

Abstract: A charging system includes: a charge port that receives shore power; a DC-to-DC converter or a motor inverter circuit; switches that connect the charge port and the DC-to-DC converter or the motor inverter circuit to battery packs; and a control module. The control module: determines open circuit voltages or states of charges of the battery packs; based on the open circuit voltages or the states of charges of the battery packs, determines whether to connect at least one of the battery packs to the charge port, the DC-to-DC converter, and the motor inverter circuit; and based on the determination of whether to connect at least one of the battery packs, control states of the switches to charge the at least one of the battery packs by selectively connecting the at least one of the battery packs to (a) the charge port, or (b) the DC-to-DC converter or motor inverter circuit.

Abstract: A method of maximizing power efficiency for a power amplifier system comprises obtaining a power supply voltage; determining a first voltage level sufficient for a power amplifier of the power amplifier system to output an output power; determining a second voltage level lower than the first voltage level; determining whether the power amplifier is activated, to generate a determination result; determining to convert the power supply voltage into a supply voltage with the first voltage level or the second voltage level according to the determination result; and supplying the power amplifier with the supply voltage.

Abstract: A semiconductor structure includes a substrate, nanostructures over the substrate, and a gate structure wrapping around the nanostructures. The gate structure includes a gate dielectric layer and a gate electrode wrapping around the gate dielectric layer. The semiconductor structure further includes a source/drain feature in contact with the nanostructures, a contact etch stop layer over the source/drain feature, and a seal layer over the air spacer and the gate structure, and on a sidewall of the contact etch stop layer. The contact etch stop layer is separated from the gate structure by an air spacer.

Abstract: A motor drive system of a vehicle includes: an inverter that receives power from a power source via a bus, where the inverter is connected to a motor of the vehicle; a driver that drives the inverter; a filter that filters a current signal received from the bus to generate a filtered signal; and a control module that operates in an impedance determination mode. The impedance determination mode includes: based on the filtered signal, controlling the driver and the inverter to generate a pulsed signal applied to the power source; determining a current level and a voltage of the power source due to generation of the pulsed signal, and determining impedance based on the current level and the voltage. The control modules are configured to: determine a characterization parameter of the power source based on the impedance; and perform a control operation or a countermeasure based on the characterization parameter.

Abstract: Disclosed in the present invention is an integrated catalyst system for stoichiometric-burn natural gas vehicles, the catalyst system consisting of a three-way catalyst, a molecular sieve catalyst, and a base body, the three-way catalyst and the molecular sieve catalyst being coated on a surface of the base body. In the integrated three-way catalyst and molecular sieve catalyst system of the present invention, at the same time that pollutants such as CO, HC, and NOx in the exhaust of stoichiometric-burn natural gas vehicles are processed, the produced byproduct NH3 can also be processed, and the conversion rates of CO, HC, NOx, and NH3 are high.

Abstract: A system for self-discharge prognostics for vehicle battery cells with an internal short circuit includes a plurality of battery cells and a voltage sensor providing open-circuit voltage data over time for each battery cell. The system further includes a computerized prognostic controller operating programming to monitor the open-circuit voltage data over time for each of the plurality of battery cells and evaluate a voltage drop rate through a time window for each of the plurality of battery cells based upon the open-circuit voltage data. The controller further identifies one of the plurality of battery cells to include the internal short circuit based upon the voltage drop rate and signals an alert based upon the one of the plurality of battery cells including the internal short circuit.

Abstract: A FinFET device structure is provided. The FinFET device structure includes a fin structure formed over a substrate, and a gate structure formed over the fin structure. The FinFET device structure includes a source/drain (S/D) structure formed over the fin structure and adjacent to the gate structure, and an S/D contact structure formed over the S/D structure and adjacent to the gate structure. The FinFET device structure also includes a protection layer formed on the S/D contact structure, and the protection layer and the S/D contact structure are made of different materials. The protection layer has a bottommost surface in direct contact with a topmost surface of the S/D contact structure.

Abstract: A semiconductor device structure is provided. The semiconductor device structure includes a source/drain region formed in a semiconductor substrate, a source/drain contact structure formed over the source/drain region, and a gate electrode layer formed adjacent to the source/drain contact structure. The semiconductor device structure also includes a first spacer and a second spacer laterally and successively arranged from the sidewall of the gate electrode layer to the sidewall of the source/drain contact structure. The semiconductor device structure further includes a silicide region formed in the source/drain region. The top width of the silicide region is greater than the bottom width of the source/drain contact structure and less than the top width of the source/drain region.

Abstract: A three-way catalyst having low NH3 formation is disclosed. The catalyst includes a carrier and a coating material. The coating material includes a precious metal active component and a catalytic material. The precious metal active component includes a first precious metal active component and a second precious metal active component. The first precious metal active component is a composition containing Ru. The second precious metal active component is a composition containing Pt, Pd and Rh. Alternatively, the second precious metal active component is a composition containing Pd and Rh.

Abstract: A glass ceramic manufactured by sequentially performing the processes of melting and thermal decomposition, water quenching and sintering of a glass composite. The glass ceramic includes 38 wt % to 49 wt % CaO, 41 wt % to 52 wt % SiO2 and 0.1 wt % to 20 wt % P2O5. The glass composite includes a glass component and P2O5, and the glass component includes CaCO3 and SiO2 and does not include an alkali metal oxide. The melting and thermal composition temperature is from 1350° C. to 1650° C. The sintering temperature is from 750° C. to 1050° C. By the combination of CaO, SiO2 and P2O5 and the control of the contents of CaO, SiO2 and P2O5 within the aforementioned ranges, and the glass ceramic contains no alkali metal oxide, the glass ceramic has good mechanical strength and low cytotoxicity.

Abstract: Disclosed here is a supported catalyst comprising a thermally stable core, wherein the thermally stable core comprises a metal oxide support and nickel disposed in the metal oxide support, wherein the metal oxide support comprises at least one base metal oxide and at least one transition metal oxide or rare earth metal oxide mixed with or dispersed in the base metal oxide. Optionally the supported catalyst can further comprise an electrolyte removing layer coating the thermally stable core and/or an electrolyte repelling layer coating the electrolyte removing layer, wherein the electrolyte removing layer comprises at least one metal oxide, and wherein the electrolyte repelling layer comprises at least one of graphite, metal carbide and metal nitride. Also disclosed is a molten carbonate fuel cell comprising the supported catalyst as a direct internal reforming catalyst.

Abstract: A semiconductor structure and the manufacturing method thereof are disclosed. An exemplary semiconductor structure includes a first source/drain contact and a second source/drain contact spaced apart by a gate structure, an etch stop layer (ESL) over the first source/drain contact and the second source/drain contact, a conductive feature disposed in the etch stop layer and in direct contact with the first source/drain contact and the second source/drain contact, a dielectric layer over the etch stop layer, and a contact via extending through the dielectric layer and electrically connected to the conductive feature. By providing the conductive feature, a number of metal lines in an interconnect structure of the semiconductor structure may be advantageously reduced.

Abstract: A semiconductor structure and a method of forming the same are provided. In an embodiment, an exemplary method of forming the semiconductor structure includes forming a fin structure extending from a front side of a substrate, recessing a source region of the fin structure to form a source opening, forming a semiconductor plug under the source opening, planarizing the substrate to expose the semiconductor plug from a back side of the substrate, performing a pre-amorphous implantation (PAI) process to amorphize the substrate, replacing the amorphized substrate with a dielectric layer, and replacing the semiconductor plug with a backside source contact. By performing the PAI process, crystalline semiconductor is amorphized and may be substantially removed. Thus, the performance and reliability of the semiconductor structure may be advantageously improved.

Abstract: Examples of an integrated circuit with an interconnect structure and a method for forming the integrated circuit are provided herein. In some examples, the method includes receiving a workpiece that includes an inter-level dielectric layer. A first contact that includes a fill material is formed that extends through the inter-level dielectric layer. The inter-level dielectric layer is recessed such that the fill material extends above a top surface of the inter-level dielectric layer. An etch-stop layer is formed on the inter-level dielectric layer such that the fill material of the first contact extends into the etch-stop layer. A second contact is formed extending through the etch-stop layer to couple to the first contact. In some such examples, the second contact physically contacts a top surface and a side surface of the first contact.

Abstract: Various embodiments of the present disclosure provide a via-first process for connecting a contact to a gate electrode. In some embodiments, the contact is formed extending through a first interlayer dielectric (ILD) layer to a source/drain region bordering the gate electrode. An etch stop layer (ESL) is deposited covering the first ILD layer and the contact, and a second ILD layer is deposited covering the ESL. A first etch is performed into the first and second ILD layers and the etch stop layer to form a first opening exposing the gate electrode. Etches are performed into the second ILD layer and the etch stop layer to form a second opening overlying the contact and overlapping the first opening, such that a bottom of the second opening slants downward from the contact to the first opening. A gate-to-contact (GC) structure is formed filling the first and second openings.