Abstract: An example operation may include one or more of identifying a newly proposed transaction of a blockchain, initiating a consensus operation to determine whether to authorize the newly proposed transaction, retrieving a key-value pair identified from a previous transaction, comparing an index value associated with the key-value pair of the previous transaction to an index value associated with a key-value pair of the newly proposed transaction, and providing an affirmative consensus to accept the newly proposed transaction in the blockchain when the index value associated with the key-value pair of the previous transaction is contiguously sequential with the index value associated with the key-value pair of the newly proposed transaction.

Abstract: Semiconductor device and the manufacturing method thereof are disclosed. An exemplary semiconductor device comprises a dielectric layer formed over a power rail; a bottom semiconductor layer formed over the dielectric layer; a backside spacer formed along a sidewall of the bottom semiconductor layer; a conductive feature contacting a sidewall of the dielectric layer and a sidewall of the backside spacer; channel semiconductor layers over the bottom semiconductor layer, wherein the channel semiconductor layers are stacked up and separated from each other; a metal gate structure wrapping each of the channel semiconductor layers; and an epitaxial source/drain (S/D) feature contacting a sidewall of each of the channel semiconductor layers, wherein the epitaxial S/D feature contacts the conductive feature, and the conductive feature contacts the power rail.

Abstract: A FinFET device structure is provided. The FinFET device structure includes a gate structure formed over a fin structure, and an S/D contact structure formed adjacent to the gate structure. The FinFET device structure includes a protection layer formed on the S/D contact structure, and an S/D conductive plug formed over the protection layer. The S/D conductive plug is electrically connected to the S/D contact structure by the protection layer.

Abstract: A semiconductor structure and a method of forming the same are provided. An exemplary method of forming the semiconductor structure includes receiving a workpiece including a fin structure over a front side of a substrate, recessing a source region of the fin structure to form a source opening, extending the source opening into the substrate to form a plug opening, forming a semiconductor plug in the plug opening, planarizing the substrate to expose the semiconductor plug from a back side of the substrate, performing a first wet etching process to remove a portion of the substrate, performing a pre-amorphous implantation (PAI) process to amorphize a rest portion of the substrate, performing a second wet etching process to remove the amorphized rest portion of the substrate to form a dielectric opening, depositing a dielectric layer in the dielectric opening, and replacing the semiconductor plug with a backside source contact.

Abstract: A mixed chemistry battery including a sensing cell having a first chemistry, a battery cell having a second chemistry that is different than the first chemistry, where the battery cell is connected to the sensing cell in series. The mixed chemistry battery also includes a battery monitoring system configured to monitor a current flow through the sensing cell and the battery cell and to calculate a state-of-charge (SOC) of the sensing cell. The battery monitoring system is further configured to calculate a SOC of the battery cell based at least in part on the SOC of the sensing cell.

Abstract: Examples of an integrated circuit with an interconnect structure and a method for forming the integrated circuit are provided herein. In some examples, the method includes receiving a workpiece that includes an inter-level dielectric layer. A first contact that includes a fill material is formed that extends through the inter-level dielectric layer. The inter-level dielectric layer is recessed such that the fill material extends above a top surface of the inter-level dielectric layer. An etch-stop layer is formed on the inter-level dielectric layer such that the fill material of the first contact extends into the etch-stop layer. A second contact is formed extending through the etch-stop layer to couple to the first contact. In some such examples, the second contact physically contacts a top surface and a side surface of the first contact.

Abstract: A system in a vehicle includes a controller to implement a neural network to provide current commands based on inputs. The inputs include a torque input. The system also includes a current controller to provide a three-phase voltage through an inverter based on the current commands from the controller. An electric traction motor provides drive power to a transmission of the vehicle based on injection of the three-phase voltage. The current commands resulting from implementation of the neural network are corrected based on estimated torque resulting from the injection of the three-phase voltage to the electric traction motor.

Abstract: A culture dish combination for embryo thawing and embryo transfer is provided. The culture dish combination includes a first culture dish and a second culture dish, the first culture dish includes a first dish cavity for thawing and laser-assisted hatching of frozen embryos, and an opening of the first dish cavity is upward. The second culture dish is detachably connected to the first culture dish, and the second culture dish includes a second dish cavity for balancing culture medium before the embryo transfer; the second culture dish further includes a third dish cavity surrounding the second dish cavity, and openings of the second dish cavity and the third dish cavity are upward. The culture dish combination solves problems of complex operations of thawing the frozen embryo, laser-assisted hatching and the embryo transfer, which increases the accuracy of the operation of embryo thawing and improves the stability of the incubator environment.

Abstract: A method includes forming a fin protruding from a substrate, forming a gate structure across the fin, forming an epitaxial feature over the fin, depositing a dielectric layer covering the epitaxial feature and over sidewalls of the gate structure, performing an etching process to form a trench, the trench dividing the gate structure into first and second gate segments and extending into a region of the dielectric layer, forming a dielectric feature in the trench, recessing a portion of the dielectric feature located in the region, selectively etching the dielectric layer to expose the epitaxial feature, and depositing a conductive feature in physical contact with the epitaxial feature and directly above the portion of the dielectric feature.

Abstract: A fiber optic imaging element includes medium-expansion and a fabrication method including: (1) matching a core glass rod with a cladding glass tube to perform mono fiber drawing; (2) arranging the mono fibers into a mono fiber bundle rod, and then drawing the mono fiber bundle rod into a multi fiber; (3) arranging the multi fiber into a multi fiber bundle rod, and then drawing the multi fiber bundle rod into a multi-multi fiber; (4) cutting the multi-multi fiber, and then arranging the multi-multi fiber into a fiber assembly buddle, then putting the fiber assembly buddle into a mold of heat press fusion process, and performing the heat press fusion process to prepare a block of the fiber optic imaging element with medium-expansion; and (5) edged rounding, cutting and slicing, face grinding and polishing the prepared medium-expansion block into a billet.

Abstract: Vias, along with methods for fabricating vias, are disclosed that exhibit reduced capacitance and resistance. An exemplary interconnect structure includes a first source/drain contact and a second source/drain contact disposed in a dielectric layer. The first source/drain contact physically contacts a first source/drain feature and the second source/drain contact physically contacts a second source/drain feature. A first via having a first via layer configuration, a second via having a second via layer configuration, and a third via having a third via layer configuration are disposed in the dielectric layer. The first via and the second via extend into and physically contact the first source/drain contact and the second source/drain contact, respectively. A first thickness of the first via and a second thickness of the second via are the same. The third via physically contacts a gate structure, which is disposed between the first source/drain contact and the second source/drain contact.

Abstract: Multiple dry etching operations are performed to form an opening for an interconnect structure, with a wet cleaning operation performed in between the dry etching operations. This multi-step etch approach increases the effectiveness of residual material removal, which increases the quality of the interconnect structure and reduces the likelihood of under etching, both of which increase semiconductor device yield and semiconductor device performance.

Abstract: Semiconductor structures and methods for manufacturing the same are provided. The method includes a gate structure formed over a substrate, and a source/drain (S/D) structure formed adjacent to the gate structure. The semiconductor structure includes a dielectric layer formed over the S/D structure, and an S/D contact structure formed over the S/D structure. The S/D contact structure is through the dielectric layer. The semiconductor structure includes a gate contact structure formed through the dielectric layer and landing on the gate structure, and the gate contact structure is in direct contact with the gate structure. The semiconductor structure includes a bridging contact structure covering the gate contact structure and the S/D contact structure, and the bottommost surface of the bridging contact structure is in direct contact with the topmost surface of the S/D contact structure.

Abstract: A semiconductor structure and a method of forming the same are provided. In an embodiment, an exemplary semiconductor structure includes a gate structure disposed over a channel region of an active region, a drain feature disposed over a drain region of the active region; a source feature disposed over a source region of the active region, a backside source contact disposed under the source feature, an isolation feature disposed on and in contact with the source feature, a drain contact disposed over and electrically coupled to the drain feature, and a gate contact via disposed over and electrically coupled to the gate structure. A distance between the gate contact via and the drain contact is greater than a distance between the gate contact via and the isolation feature. The exemplary semiconductor structure would have a reduced parasitic capacitance and an enlarged leakage window.

Abstract: In an embodiment, a method includes: forming a first fin extending from a substrate; forming a second fin extending from the substrate, the second fin being spaced apart from the first fin by a first distance; forming a metal gate stack over the first fin and the second fin; depositing a first inter-layer dielectric over the metal gate stack; and forming a gate contact extending through the first inter-layer dielectric to physically contact the metal gate stack, the gate contact being laterally disposed between the first fin and the second fin, the gate contact being spaced apart from the first fin by a second distance, where the second distance is less than a second predetermined threshold when the first distance is greater than or equal to a first predetermined threshold.

Abstract: A semiconductor structure includes a source/drain (S/D) feature disposed in a semiconductor layer, a metal gate stack (MG) disposed in a first interlayer dielectric (ILD) layer and adjacent to the S/D feature, a second ILD layer disposed over the MG, and an S/D contact disposed over the S/D feature. The semiconductor structure further includes an air gap disposed between a sidewall of a bottom portion of the S/D contact and the first ILD layer, where a sidewall of a top portion of the S/D contact is in direct contact with the second ILD layer.

Abstract: A method for detecting thermal runaway of a cell includes: positioning a battery pack having multiple cells in an automobile vehicle; measuring a cell voltage of the multiple cells at a predetermined sample rate; and identifying if the cell voltage decreases and modulates coincident with a cell surface temperature increase indicating initiation of a cell short.

Abstract: A method of semiconductor fabrication includes providing a semiconductor structure having a substrate and first, second, third, and fourth fins above the substrate. The method further includes forming an n-type epitaxial source/drain (S/D) feature on the first and second fins, forming a p-type epitaxial S/D feature on the third and fourth fins, and performing a selective etch process on the semiconductor structure to remove upper portions of the n-type epitaxial S/D feature and the p-type epitaxial S/D feature such that more is removed from the n-type epitaxial S/D feature than the p-type epitaxial S/D feature.

Abstract: Techniques for business data protection for running tasks in a computer system are described herein. An aspect includes receiving a request. Another aspect includes processing a task corresponding to the request. Another aspect includes receiving a debugging request from a user corresponding to the task, wherein the debugging request is received during the processing of the task. Another aspect includes, based on receiving the debugging request, determining whether the user is authorized to access business data corresponding to the task. Another aspect includes, based on determining that the user is not authorized to access the business data corresponding to the task, redacting the business data from debugging data corresponding to the debugging request. Another aspect includes providing the redacted debugging data to the user.

Abstract: In accordance with the implementations of the subject matter described herein, there is provided a solution for reusing infographics. In this solution, a group of visual element units is determined from a visual element set comprised in the original infographic. A visual element unit in the group represents an information item in the original infographic. A first correlation between a visual element contained in the visual element unit and the information item and a second correlation between the visual element unit and a further visual element unit in the group are determined. A description for the original infographic is generated based on the first and second correlations. A target infographic is generated by updating the group of visual element units at least based on the description and the target information. In this way, infographics can be converted into reusable templates, thereby simplifying reuse of such infographics and improving user experience.