Abstract: A semiconductor device includes an active region that extends in a first horizontal direction. A source/drain component is disposed over the active region. A source/drain contact is disposed over the source/drain component. A gate structure is disposed over the active region. The gate structure extends in a second horizontal direction different from the first horizontal direction. Side surfaces of the source/drain contact are substantially more tapered in the second horizontal direction than in the first horizontal direction.

Abstract: A supervisory computer is used with an energy management system of an electric vehicle. The energy management system includes a battery system having a plurality of battery subsystems. One of the battery subsystems is an abnormal battery subsystem while the remaining battery subsystems are normal battery subsystems. The supervisory computer includes at least one processor and at least one non-transitory computer-readable medium. The processor monitors the remaining state of charge, capacity, and resistance of the battery system and monitor the remaining state of charge and capacity of the abnormal battery subsystem, calculate a low integration bound value, calculate a remaining energy value for all of the normal battery subsystems with respect to the low integration value, calculate a remaining energy value for the abnormal battery subsystem, and summate the remaining energy values of the normal and abnormal battery subsystems to determine a global remaining energy value for the battery system.

Abstract: A semiconductor device structure and a method for forming a semiconductor device structure are provided. The semiconductor device structure includes a metal gate stack over a substrate and an epitaxial structure over the substrate. The semiconductor device structure also includes a conductive contact electrically connected to the epitaxial structure. A topmost surface of the metal gate stack is vertically disposed between a topmost surface of the conductive contact and a bottommost surface of the conductive contact. The semiconductor device structure further includes a first conductive via electrically connected to the metal gate stack. The topmost surface of the conductive contact is vertically disposed between a topmost surface of the first conductive via and a bottommost surface of the first conductive via. In addition, the semiconductor device structure includes a second conductive via electrically connected to the conductive contact.

Abstract: A semiconductor structure and a method of forming the same are provided. In an embodiment, a semiconductor structure includes a first plurality of channel members over a backside dielectric layer, a second plurality of channel members over the backside dielectric layer, a silicide feature disposed in the backside dielectric layer, and a source/drain feature disposed over the silicide feature and extending between the first plurality of channel members and the second plurality of channel members. The silicide feature extends through an entire depth of the backside dielectric layer.

Abstract: A method for calibrating the alignment of a wafer is provided. A plurality of alignment position deviation (APD) simulation results are obtained form a plurality of mark profiles. An alignment analysis is performed on a mark region of the wafer with a light beam. A measured APD of the mark region of the wafer is obtained in response to the light beam. The measured APD is compared with the APD simulation results to obtain alignment calibration data. An exposure process is performed on the wafer with a mask according to the alignment calibration data.

Abstract: A vehicle includes a system operating a method of controlling a temperature at a battery cell of the vehicle. The system includes the battery cell, a temperature sensor and a processor. The battery cell has a tab for flow of current to and from the battery cell. The temperature sensor is configured to measure a cell temperature of the battery cell at a location away from the tab. The processor is configured to predict a tab temperature from the cell temperature, and control a power supplied to a load from the battery cell based on the tab temperature.

Abstract: A method of manufacturing a display substrate which includes a central display area and an arc-shaped stretch area located at a corner of the central display area, wherein the method includes: preparing a substrate to be etched, which includes a flexible substrate, a stack structure disposed on the flexible substrate, and a last-dry-etched metal layer disposed on a side of the stack structure away from the flexible substrate, the stack structure including an active layer, at least one conductive layer, and a plurality of insulating layers, wherein the last-dry-etched metal layer is a last metal layer that is formed through dry etching; and forming a stretch groove by patterning the substrate to be etched, wherein the stretch groove is disposed in the stretch area and passes through the stack structure and a part of the flexible substrate. A display substrate, a display panel and a display device are further provided.

Abstract: A lighting apparatus includes a LED module, a light source plate, a heat sink, an antenna, a driver and a light housing. The light source plate is used for holding the LED module. The heat sink has a bottom plate and a lateral wall. The light source plate is placed on the bottom plate. The antenna is disposed on the lateral wall. The driver is used for generating a driving current to the LED module. The driver has a wireless circuit. The wireless circuit is electrically connected to the antenna for transmitting a wireless signal. The light housing is used for holding the heat sink so that the LED module emits light toward a light opening of the light housing.

Abstract: A new method for extracting lithium from salt lake brine, comprising the following steps: a salt lake old brine raw material, desorption liquid, low-magnesium water, and adsorption tail liquid pass through an old brine feeding pipe (2), a desorption liquid feeding pipe (4), a low-magnesium water top desorption liquid feeding pipe (3), and an adsorption tail liquid top desorption liquid feeding pipe (11), respectively, which are located above and below a rotary disc of a multi-way valve system (1); and after respectively entering corresponding adsorption columns (6) by means of a duct and channel within the multi-way valve system (1), the entire process procedure is completed from an adsorption tail liquid discharge pipe (7), a qualified desorption liquid discharge pipe (10), a lithium-containing old brine discharge pipe (8), and an adsorption tail liquid top desorption liquid discharge pipe (5); and the adsorption columns (6) are connected in series or in parallel by means of channels located in the multi-way

Abstract: An ozone purification catalyst, and a preparation method therefor and an application thereof are provided. The catalyst coating uses macroporous, high specific surface and CeO2 and/or La2O3 modified Al2O3 as the carrier material, and Mn and/or Pd as the active component. The preparation method is to prepare the Al2O3-based material by a sol-gel method, and then to load the active components on the carrier material, and to dry, calcinate and solidify to obtain the ozone purification catalyst. The catalysts as prepared shows a fast and efficient purification of ozone. The complete conversion temperature covers a wide range of temperature. The catalyst has excellent texture performance, high specific surface area and large pore volume, which is beneficial to ozone purification when the car is running at high speed. The particle sizes and colors of the catalyst can be modified according to various requirements.

Abstract: In an embodiment, a method includes: forming a differential contact etch stop layer (CESL) having a first portion over a source/drain region and a second portion along a gate stack, the source/drain region being in a substrate, the gate stack being over the substrate proximate the source/drain region, a first thickness of the first portion being greater than a second thickness of the second portion; depositing a first interlayer dielectric (ILD) over the differential CESL; forming a source/drain contact opening in the first ILD; forming a contact spacer along sidewalls of the source/drain contact opening; after forming the contact spacer, extending the source/drain contact opening through the differential CESL; and forming a first source/drain contact in the extended source/drain contact opening, the first source/drain contact physically and electrically coupling the source/drain region, the contact spacer physically separating the first source/drain contact from the first ILD.

Abstract: Vias, along with methods for fabricating vias, are disclosed that exhibit reduced capacitance and resistance. An exemplary interconnect structure includes a first source/drain contact and a second source/drain contact disposed in a dielectric layer. The first source/drain contact physically contacts a first source/drain feature and the second source/drain contact physically contacts a second source/drain feature. A first via having a first via layer configuration, a second via having a second via layer configuration, and a third via having a third via layer configuration are disposed in the dielectric layer. The first via and the second via extend into and physically contact the first source/drain contact and the second source/drain contact, respectively. A first thickness of the first via and a second thickness of the second via are the same. The third via physically contacts a gate structure, which is disposed between the first source/drain contact and the second source/drain contact.

Abstract: A semiconductor structure includes a metal gate structure comprising a gate dielectric layer and a gate electrode, a conductive layer disposed over the metal gate structure, and a contact feature in direct contact with the top portion of the conductive layer, where the conductive layer includes a bottom portion disposed below a top surface of the metal gate structure and a top portion disposed over the top surface of the metal gate structure, and where the top portion laterally extends beyond a sidewall of the bottom portion.

Abstract: A patient support apparatus includes a bed including a frame. A mattress is supported by the frame. A respiratory therapy apparatus is supported by the frame. A pneumatic system is operable to inflate at least one bladder of the mattress and operable to deliver air to the respiratory therapy apparatus.

Abstract: A semiconductor structure includes an isolation feature disposed over a semiconductor substrate, a semiconductor fin disposed over the semiconductor substrate and adjacent to the isolation feature, a source/drain (S/D) feature disposed over the semiconductor substrate and apart from the isolation feature, an interlayer dielectric (ILD) layer disposed over the isolation feature and the S/D feature, a first contact plug disposed in the ILD layer and over the isolation feature, a second contact plug disposed in the ILD layer and over the S/D feature, and a dielectric layer between surfaces of the first contact plug and the ILD layer and between a sidewall of the second contact plug and the ILD layer, where a bottom surface of the second contact plug is free of the dielectric layer.

Abstract: Semiconductor structures and methods for manufacturing the same are provided. The method for manufacturing the semiconductor structure includes forming a gate structure over a substrate and forming a mask layer covering the gate structure. The method also includes forming a source/drain structure adjacent to the gate structure over the substrate and forming a contact over the source/drain structure. The method also includes forming a dielectric layer over the contact and the mask layer and forming a first trench through the dielectric layer and the mask layer over the gate structure. The method also includes forming a first conductive structure in the first trench and removing an upper portion of the first conductive structure. The method also includes forming a second conductive structure through the dielectric layer and covering the contact and the first conductive structure.

Abstract: A method includes forming a first conductive feature over a semiconductor substrate, forming an ILD layer over the first conductive feature, patterning the ILD layer to form a trench, and forming a conductive layer over the patterned ILD layer to fill the trench. The method further includes polishing the conductive layer to form a via contact configured to interconnect the first conductive feature with a second conductive feature, where polishing the conductive layer exposes a top surface of the ILD layer, polishing the exposed top surface of the ILD layer, such that a top portion of the via contact protrudes from the exposed top surface of the ILD layer, and forming the second conductive feature over the via contact, such that the top portion of the via contact extends into the second conductive feature.

Abstract: In an embodiment, a device includes: a semiconductor substrate; a first fin extending from the semiconductor substrate; a second fin extending from the semiconductor substrate; an epitaxial source/drain region including: a main layer in the first fin and the second fin, the main layer including a first semiconductor material, the main layer having an upper faceted surface and a lower faceted surface, the upper faceted surface and the lower faceted surface each being raised from respective surfaces of the first fin and the second fin; and a semiconductor contact etch stop layer (CESL) contacting the upper faceted surface and the lower faceted surface of the main layer, the semiconductor CESL including a second semiconductor material, the second semiconductor material being different from the first semiconductor material.

Abstract: An integrated circuit includes a substrate, an isolation feature disposed over the substrate, a fin extending from the substrate above the isolation feature, and a gate structure disposed directly over the isolation feature. The integrated circuit further includes a first dielectric layer disposed directly above the isolation feature and adjacent to the gate structure, and a first etch stop layer disposed between the first dielectric layer and the isolation feature. The integrated circuit further includes a second dielectric layer disposed directly above the first dielectric layer, and a second etch stop layer disposed between the first and the second dielectric layers and between the gate structure and the second dielectric layer. The first etch stop layer is also disposed between the gate structure and the second etch stop layer. A conductive feature is directly above the isolation feature and directly contacting the first dielectric layer.

Abstract: Embodiments of the present disclosure relate to a solution for translation verification and correction. According to the solution, a neural network is trained to determine an association degree among a group of words in a source or target language. The neural network can be used for translation verification and correction. According to the solution, a group of words in a source language and translations of the group of words in a target language are obtained. An association degree among the group of words and an association degree among the translations can be determined by using the trained neural network. Then, whether there is a wrong translation can be determined based on the association degrees. In some embodiments, corresponding methods, systems and computer program products are provided.