Abstract: A semiconductor device includes a gate structure disposed over a substrate, and a first dielectric layer disposed over the substrate, including and over the gate structure. A first metal feature is disposed in the first dielectric layer, including an upper portion having a first width and a lower portion having a second width that is different than the first width. A dielectric spacer is disposed along the lower portion of the first metal feature, wherein the upper portion of the first metal feature is disposed over the dielectric spacer. A second dielectric layer is disposed over the first dielectric layer, including over the first metal feature and a second metal feature extends through the second dielectric layer to physically contact with the first metal feature. A third metal feature extends through the second dielectric layer and the first dielectric layer to physically contact the gate structure.

Abstract: A method of taking an elevator by an unmanned device is provided including: through a remote communication connection established with a cloud platform, sending a start floor elevator call request to the cloud platform; receiving real-time running information of at least one elevator returned by the cloud platform; selecting a target elevator according to the real-time running information of the at least one elevator, and entering the target elevator; and establishing a communication connection with an elevator controlling communication device of the target elevator, and sending a target floor elevator call request to an elevator controlling device of the target elevator through the communication connection such that the elevator controlling device controls the target elevator to run to a target floor based on the target floor elevator call request, where the elevator controlling communication device of the target elevator is connected with the elevator controlling device of the target elevator.

Abstract: A lamp has a safety circuit connected to first and second electrical connection terminals. A test is used to detect if the first and second electrical connection terminals are both connected to external power without an interfering impedance such a human body, and only then enable operation of the lamp. A time for the test is different from a time when another lamp in the system applies a test.

Abstract: Various embodiments of the present disclosure provide a via-first process for connecting a contact to a gate electrode. In some embodiments, the contact is formed extending through a first interlayer dielectric (ILD) layer to a source/drain region bordering the gate electrode. An etch stop layer (ESL) is deposited covering the first ILD layer and the contact, and a second ILD layer is deposited covering the ESL. A first etch is performed into the first and second ILD layers and the etch stop layer to form a first opening exposing the gate electrode. A series of etches is performed into the second ILD layer and the etch stop layer to form a second opening overlying the contact and overlapping the first opening, such that a bottom of the second opening slants downward from the contact to the first opening. A gate-to-contact (GC) structure is formed filling the first and second openings.

Abstract: The invention provides a probabilistic wind speed forecasting method and system based on multi-scale information. First, a convolutional neural network (CNN) model with multiple convolutional layers is employed for extracting multi-scale features (MSFs). Then, an attention-based long short-term memory (LSTM) is utilized to extract temporal characteristics from the features at each scale and encode them into a low-dimensional feature vector. The difference between the conditional quantiles of adjacent quantiles is obtained with the proposed non-crossing quantile loss, and the estimates of all the conditional quantiles can be calculated by accumulating and subtracting. The proposed invention can extract sufficient MSFs from limited data, provide high-quality and reliable probabilistic forecasts, and solve the crossing problem of quantile-based models.

Abstract: An application of MAL33 gene deletion in improving the tolerance of Saccharomyces cerevisiae to inhibitors in a lignocellulose hydrolyzate is provided. The tolerance of the present MAL33 gene-deleted Saccharomyces cerevisiae strain to acetic acid is greatly improved, and the tolerance of the Saccharomyces cerevisiae strain to other typical inhibitors and H2O2 in the lignocellulose hydrolyzate is also improved. The lag period of the Saccharomyces cerevisiae strain in a glucose and xylose medium (YPDX) with 3.5 g/L acetic acid is shortened by 24 h. The fermentation period of the Saccharomyces cerevisiae strain to produce ethanol through co-utilization of glucose and xylose is shortened by 20 h. The growth of the Saccharomyces cerevisiae strain in a glucose and xylose medium (YPDX) with a mixed inhibitor and the ethanol production of the Saccharomyces cerevisiae strain through the co-fermentation of glucose and xylose are superior to those of a control strain.

Abstract: A display pixel is provided that is operable to support hybrid compensation scheme having both in-pixel threshold voltage canceling and external threshold voltage compensation. The display may include multiple p-type silicon transistors with at least one n-type semiconducting-oxide transistor and one storage capacitor. An on-bias stress phase may be performed prior to a threshold voltage sampling and data programming phase to mitigate hysteresis and improve first frame response. In low refresh rate displays, a first additional on-bias stress operation can be performed separate from the threshold voltage sampling and data programming phase during a refresh frame and a second additional on-bias stress operation can be performed during a vertical blanking frame. The display pixel may be configured to receive an initialization voltage and an anode reset voltage, either of which can be dynamically tuned to match the stress of the first and second additional on-bias stress operations to minimize flicker.

Abstract: A battery system for a vehicle includes a plurality of battery modules, each of the plurality of battery modules including a respective management module, and a master management module configured to communicate with the management modules and with a battery control module. Each of the management modules includes a communication interface configured to transmit data to the master management module and receive data from the master management module and a diagnostic module configured to monitor operating parameters of a respective one of the plurality of battery modules, detect a fault associated with the respective one of the plurality of battery modules based on the operating parameters, and selectively output a signal indicative of the detected fault.

Abstract: A monitoring system for a battery system includes a battery system including a battery pack. The battery pack includes M battery modules, where M is an integer greater than zero. Each of the M battery modules includes C battery cells, where C is an integer greater than one. T temperature sensors configured to generate sensed temperatures of the M battery modules, where T is greater than or equal to M and less than M times C. A battery management module configured to perform battery impedance measurements on the C battery cells of the M battery modules; generate estimated temperatures for each of the C battery cells of the M battery modules based on the battery impedance measurements; and selectively detect at least one of the C battery cells having a cell outlier temperature based on the estimated temperatures of the C battery cells.

Abstract: A method of forming a semiconductor device structure is provided. The method includes forming an insulating layer over a semiconductor substrate including a conductive feature, forming an insulating layer with a trench over the semiconductor substrate to expose the conductive feature, and forming a sacrificial liner layer over two opposite sidewalls and a bottom of the trench. Ions are implanted into the conductive feature covered by the sacrificial liner layer, so that a doping region is formed in the conductive feature and has two opposite side edges respectively separated from the two opposite sidewalls of the trench. The sacrificial liner layer is removed after forming the doping region, and a conductive connecting structure is formed in the trench. The two opposite sidewalls of the conductive connecting structure are respectively separated from the two corresponding opposite sidewalls of the trench by an air spacer.

Abstract: A semiconductor structure and the manufacturing method thereof are disclosed. An exemplary semiconductor structure includes a first source/drain contact and a second source/drain contact spaced apart by a gate structure, an etch stop layer (ESL) over the first source/drain contact and the second source/drain contact, a conductive feature disposed in the etch stop layer and in direct contact with the first source/drain contact and the second source/drain contact, a dielectric layer over the etch stop layer, and a contact via extending through the dielectric layer and electrically connected to the conductive feature. By providing the conductive feature, a number of metal lines in an interconnect structure of the semiconductor structure may be advantageously reduced.

Abstract: A device for double-sided processing through single shot peening includes: a shot peening system, a workpiece clamping mechanism for clamping a workpiece, and a rebound system. The workpiece is provided with a first through-hole, and the first through-hole directly faces a nozzle. The rebound system includes a reflecting surface, an open container, and a reflecting surface gripping unit. The reflecting surface includes an upper reflecting surface, a middle reflecting surface, and a lower reflecting surface. The middle reflecting surface is provided with a second through-hole. The upper reflecting surface and the lower reflecting surface are both made of flexible elastic materials and are both provided with waterproof layers. A partition plate is disposed in the open container and partitions the open container into a first cavity and a second cavity. The second cavity is provided with a filling liquid, and the partition plate is slidable in the open container.

Abstract: A method for forming a semiconductor device includes forming a metal gate stack having a gate dielectric layer and a gate electrode disposed over the gate dielectric layer. The gate electrode includes a first metal layer and a second metal layer. The method further includes performing a plasma treatment to a top surface of the metal gate stack and forming a conductive layer over the treated top surface of the metal gate stack. A top portion of the conductive layer is formed above a top surface of the gate dielectric layer, and a bottom portion of the conductive layer penetrates into the first and the second metal layers of the gate electrode at different distances.

Abstract: A displaying base plate includes an opening region, an adjacent region surrounding the opening region, and a displaying region surrounding the adjacent region, and the displaying base plate located within the adjacent region includes: a substrate base plate; a flat layer and a passivation layer that are provided on one side of the substrate base plate, wherein the passivation layer is provided on one side of the flat layer that is further away from the substrate base plate, a surface of the one side of the flat layer that is further away from the substrate base plate includes at least an inclined plane adjacent to one side of the opening region, and the flat layer includes a first protrusion provided on the inclined plane; and a first isolating groove that at least partially overlaps with the first protrusion and extends throughout the passivation layer and extends into the first protrusion.

Abstract: An integrated circuit structure in which a gate overlies channel region in an active area of a first transistor. The first transistor includes a channel region, a source region and a drain region. A conductive contact is coupled to the drain region of the first transistor. A second transistor that includes a channel region, a source region a drain region is adjacent to the first transistor. The gate of the second transistor is spaced from the gate of the first transistor. A conductive via passes through an insulation layer to electrically connect to the gate of the second transistor. An expanded conductive via overlays both the conductive contact and the conductive via to electrically connect the drain of the first transistor to the gate of the second transistor.

Abstract: A method is disclosed for determining the state of health of an electric battery that includes a plurality of battery cells. The method includes the steps of measuring the cell voltage of each individual cell of the plurality of battery cells, and analyzing each measured battery cell voltage to determine the state of health of the corresponding battery cell.

Abstract: A semiconductor structure and a method of forming the same are provided. In an embodiment, a semiconductor structure includes a first plurality of channel members over a backside dielectric layer, a second plurality of channel members over the backside dielectric layer, a silicide feature disposed in the backside dielectric layer, and a source/drain feature disposed over the silicide feature and extending between the first plurality of channel members and the second plurality of channel members. The silicide feature extends through an entire depth of the backside dielectric layer.

Abstract: A lighting apparatus includes a LED module, a light source plate, a heat sink, an antenna, a driver and a light housing. The light source plate is used for holding the LED module. The heat sink has a bottom plate and a lateral wall. The light source plate is placed on the bottom plate. The antenna is disposed on the lateral wall. The driver is used for generating a driving current to the LED module. The driver has a wireless circuit. The wireless circuit is electrically connected to the antenna for transmitting a wireless signal. The light housing is used for holding the heat sink so that the LED module emits light toward a light opening of the light housing.

Abstract: A low-temperature NOx storage catalyst for automobile exhaust purification and a preparation method thereof. Loading a noble metal salt solution on molecular sieve by equal volume impregnation method, wherein the noble metal salt solution comprises palladium nitrate and platinum nitrate, and the molecular sieve comprises SSZ, SAPO and BETA, then drying at 60-120° C. for 2-6 h, roasting at 500-550° C. in air for 2-5 h, and further roasting at 750-850° C. in air for 2-5 h, and then mixing with aluminum sol, ball milling and pulping, and then coating the slurry on a carrier, wherein the loading on the coating is 100-250 g/L and the noble metal content is 10-150 g/ft3, drying at 60-120° C. for 2-6 h, then roasting at 500-550° C. in air for 2-5 h, and further continuing roasting at 750-850° C. in air for 2-5 h, to obtain the catalyst.

Abstract: An embodiment method includes: forming fins extending from a semiconductor substrate; depositing an inter-layer dielectric (ILD) layer on the fins; forming masking layers on the ILD layer; forming a cut mask on the masking layers, the cut mask including a first dielectric material, the cut mask having first openings exposing the masking layers, each of the first openings surrounded on all sides by the first dielectric material; forming a line mask on the cut mask and in the first openings, the line mask having slot openings, the slot openings exposing portions of the cut mask and portions of the masking layers, the slot openings being strips extending perpendicular to the fins; patterning the masking layers by etching the portions of the masking layers exposed by the first openings and the slot openings; and etching contact openings in the ILD layer using the patterned masking layers as an etching mask.