Patents by Inventor Yun Wang

Yun Wang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11694931
    Abstract: A semiconductor device includes a substrate, first and second fins protruding from the substrate, and first and second source/drain (S/D) features over the first and second fins respectively. The semiconductor device further includes an isolation feature over the substrate and disposed between the first and second S/D features, and a dielectric layer disposed on sidewalls of the first and second S/D features and on sidewalls of the isolation feature. A top portion of the isolation feature extends above the dielectric layer.
    Type: Grant
    Filed: February 22, 2021
    Date of Patent: July 4, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD
    Inventors: I-Wen Wu, Chen-Ming Lee, Fu-Kai Yang, Mei-Yun Wang, Chang-Yun Chang, Ching-Feng Fu, Peng Wang
  • Publication number: 20230206536
    Abstract: Implementations of the subject matter described herein relate to generating animated infographics from static infographics. A computer-implemented method comprises: extracting visual elements of a static infographic; determining, based on the visual elements, a structure of the static infographic at least indicating a layout of the visual elements in the static infographic; and applying a dynamic effect to the visual elements based on the structure of the static infographic to generate an animated infographic.
    Type: Application
    Filed: May 9, 2021
    Publication date: June 29, 2023
    Inventors: Yun Wang, He Huang, Haidong Zhang
  • Publication number: 20230204369
    Abstract: A trip energy estimation system includes a memory and a control module. The memory stores average traffic speed, average traffic acceleration, driver speed, and driver acceleration data. The control module executes an algorithm to estimate an amount of energy for an electric vehicle to travel between two locations. The algorithm includes: determining, based on the average traffic speed data and the average traffic acceleration data, a baseline amount of energy for the electric vehicle to travel between the two locations; determining, based on the driver speed data and the driver acceleration data, a dynamic amount of energy corresponding to at least one of stop and go events, over speeding, or under speeding; and determining a total amount of energy based on the baseline amount of energy and the dynamic amount of energy. The control module, based on the total amount of energy, performs an operation including indicating a trip estimate.
    Type: Application
    Filed: December 27, 2021
    Publication date: June 29, 2023
    Inventors: Yue-Yun WANG, Dongxu LI, Brandon D. MAZZARA, Jonathan WILSON, Chen-Fang CHANG, Chunhao J. LEE
  • Publication number: 20230205359
    Abstract: A method for reporting touch on a touchscreen includes detecting first touch data from the touchscreen corresponding to a first touch on the touchscreen; determining coordinates of the first touch from the first touch data; reporting the coordinates of the first touch at a first time; determining predicted coordinates of a second touch based on a linear regression of historical touch data; and reporting the predicted coordinates of the second touch at a second time, where the second time occurs after the first time.
    Type: Application
    Filed: December 27, 2021
    Publication date: June 29, 2023
    Inventors: Yuan Yun Wang, Pengcheng Wen, Yingying Sun, Yue Ding
  • Publication number: 20230197802
    Abstract: A method according to the present disclosure includes forming a fin-shaped structure protruding from a substrate, forming a gate structure intersecting the fin-shaped structure, forming a gate spacer on a sidewall of the gate structure, and forming a conductive feature above the fin-shaped structure. The gate spacer is laterally between the gate structure and the conductive feature. The method also includes depositing a dielectric layer over the gate structure and the conductive feature, performing an etching process, thereby forming an opening through the dielectric layer and exposing top surfaces of the conductive feature and the gate structure, recessing the gate spacers through the opening, thereby exposing the sidewall of the gate structure, and forming a contact feature in the opening, wherein the contact feature is in contact with the conductive feature and has a bottom portion protruding downward to be in contact with the sidewall of the gate structure.
    Type: Application
    Filed: June 4, 2022
    Publication date: June 22, 2023
    Inventors: Jui-Lin Chen, Chao-Hsun Wang, Hsin-Wen Su, Yi-Feng Ting, Chi Hua Wang, I-Hung Li, Yuan-Tien Tu, Fu-Kai Yang, Mei-Yun Wang, Ping-Wei Wang, Lien Jung Hung
  • Patent number: 11682579
    Abstract: A semiconductor device includes a gate structure disposed over a substrate, and a first dielectric layer disposed over the substrate, including and over the gate structure. A first metal feature is disposed in the first dielectric layer, including an upper portion having a first width and a lower portion having a second width that is different than the first width. A dielectric spacer is disposed along the lower portion of the first metal feature, wherein the upper portion of the first metal feature is disposed over the dielectric spacer. A second dielectric layer is disposed over the first dielectric layer, including over the first metal feature and a second metal feature extends through the second dielectric layer to physically contact with the first metal feature. A third metal feature extends through the second dielectric layer and the first dielectric layer to physically contact the gate structure.
    Type: Grant
    Filed: May 27, 2022
    Date of Patent: June 20, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD
    Inventors: Chao-Hsun Wang, Hsien-Cheng Wang, Mei-Yun Wang
  • Patent number: 11682729
    Abstract: A semiconductor structure includes a source/drain (S/D) feature disposed in a semiconductor layer, a metal gate stack (MG) disposed in a first interlayer dielectric (ILD) layer and adjacent to the S/D feature, a second ILD layer disposed over the MG, and an S/D contact disposed over the S/D feature. The semiconductor structure further includes an air gap disposed between a sidewall of a bottom portion of the S/D contact and the first ILD layer, where a sidewall of a top portion of the S/D contact is in direct contact with the second ILD layer.
    Type: Grant
    Filed: January 14, 2022
    Date of Patent: June 20, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Chao-Hsun Wang, Chen-Ming Lee, Kuo-Yi Chao, Mei-Yun Wang, Pei-Yu Chou, Kuo-Ju Chen
  • Publication number: 20230174341
    Abstract: A method of taking an elevator by an unmanned device is provided including: through a remote communication connection established with a cloud platform, sending a start floor elevator call request to the cloud platform; receiving real-time running information of at least one elevator returned by the cloud platform; selecting a target elevator according to the real-time running information of the at least one elevator, and entering the target elevator; and establishing a communication connection with an elevator controlling communication device of the target elevator, and sending a target floor elevator call request to an elevator controlling device of the target elevator through the communication connection such that the elevator controlling device controls the target elevator to run to a target floor based on the target floor elevator call request, where the elevator controlling communication device of the target elevator is connected with the elevator controlling device of the target elevator.
    Type: Application
    Filed: May 14, 2021
    Publication date: June 8, 2023
    Inventors: Yun WANG, Jie SHI, Kang SUN, Suchen MA, Pengyu HAN
  • Patent number: 11672073
    Abstract: A lamp has a safety circuit connected to first and second electrical connection terminals. A test is used to detect if the first and second electrical connection terminals are both connected to external power without an interfering impedance such a human body, and only then enable operation of the lamp. A time for the test is different from a time when another lamp in the system applies a test.
    Type: Grant
    Filed: December 17, 2019
    Date of Patent: June 6, 2023
    Assignee: SIGNIFY HOLDING B.V.
    Inventors: Xiajuan Wu, Dalibor Cvoric, Ye Liu, Haimin Tao, Yun Wang, Han Lu, Jing Yang, Deyong Kong, Jing Li
  • Patent number: 11670544
    Abstract: Various embodiments of the present disclosure provide a via-first process for connecting a contact to a gate electrode. In some embodiments, the contact is formed extending through a first interlayer dielectric (ILD) layer to a source/drain region bordering the gate electrode. An etch stop layer (ESL) is deposited covering the first ILD layer and the contact, and a second ILD layer is deposited covering the ESL. A first etch is performed into the first and second ILD layers and the etch stop layer to form a first opening exposing the gate electrode. A series of etches is performed into the second ILD layer and the etch stop layer to form a second opening overlying the contact and overlapping the first opening, such that a bottom of the second opening slants downward from the contact to the first opening. A gate-to-contact (GC) structure is formed filling the first and second openings.
    Type: Grant
    Filed: November 23, 2021
    Date of Patent: June 6, 2023
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chao-Hsun Wang, Mei-Yun Wang, Kuo-Yi Chao, Wang-Jung Hsueh
  • Publication number: 20230169230
    Abstract: The invention provides a probabilistic wind speed forecasting method and system based on multi-scale information. First, a convolutional neural network (CNN) model with multiple convolutional layers is employed for extracting multi-scale features (MSFs). Then, an attention-based long short-term memory (LSTM) is utilized to extract temporal characteristics from the features at each scale and encode them into a low-dimensional feature vector. The difference between the conditional quantiles of adjacent quantiles is obtained with the proposed non-crossing quantile loss, and the estimates of all the conditional quantiles can be calculated by accumulating and subtracting. The proposed invention can extract sufficient MSFs from limited data, provide high-quality and reliable probabilistic forecasts, and solve the crossing problem of quantile-based models.
    Type: Application
    Filed: September 5, 2022
    Publication date: June 1, 2023
    Inventors: Yun Wang, Mengmeng Song, Runmin Zou, Daoguang He
  • Publication number: 20230151348
    Abstract: An application of MAL33 gene deletion in improving the tolerance of Saccharomyces cerevisiae to inhibitors in a lignocellulose hydrolyzate is provided. The tolerance of the present MAL33 gene-deleted Saccharomyces cerevisiae strain to acetic acid is greatly improved, and the tolerance of the Saccharomyces cerevisiae strain to other typical inhibitors and H2O2 in the lignocellulose hydrolyzate is also improved. The lag period of the Saccharomyces cerevisiae strain in a glucose and xylose medium (YPDX) with 3.5 g/L acetic acid is shortened by 24 h. The fermentation period of the Saccharomyces cerevisiae strain to produce ethanol through co-utilization of glucose and xylose is shortened by 20 h. The growth of the Saccharomyces cerevisiae strain in a glucose and xylose medium (YPDX) with a mixed inhibitor and the ethanol production of the Saccharomyces cerevisiae strain through the co-fermentation of glucose and xylose are superior to those of a control strain.
    Type: Application
    Filed: October 10, 2022
    Publication date: May 18, 2023
    Applicant: Qilu University of Technology (Shandong Academy of Sciences)
    Inventors: Lili XU, Xiaoming BAO, Yun WANG, Tianqing XIA, Chenhao LI, Fangqing WEI, Ai YUAN
  • Patent number: 11651736
    Abstract: A display pixel is provided that is operable to support hybrid compensation scheme having both in-pixel threshold voltage canceling and external threshold voltage compensation. The display may include multiple p-type silicon transistors with at least one n-type semiconducting-oxide transistor and one storage capacitor. An on-bias stress phase may be performed prior to a threshold voltage sampling and data programming phase to mitigate hysteresis and improve first frame response. In low refresh rate displays, a first additional on-bias stress operation can be performed separate from the threshold voltage sampling and data programming phase during a refresh frame and a second additional on-bias stress operation can be performed during a vertical blanking frame. The display pixel may be configured to receive an initialization voltage and an anode reset voltage, either of which can be dynamically tuned to match the stress of the first and second additional on-bias stress operations to minimize flicker.
    Type: Grant
    Filed: February 24, 2022
    Date of Patent: May 16, 2023
    Assignee: Apple Inc.
    Inventors: Chin-Wei Lin, Shinya Ono, Zino Lee, Yun Wang, Fan Gui
  • Publication number: 20230148115
    Abstract: A battery system for a vehicle includes a plurality of battery modules, each of the plurality of battery modules including a respective management module, and a master management module configured to communicate with the management modules and with a battery control module. Each of the management modules includes a communication interface configured to transmit data to the master management module and receive data from the master management module and a diagnostic module configured to monitor operating parameters of a respective one of the plurality of battery modules, detect a fault associated with the respective one of the plurality of battery modules based on the operating parameters, and selectively output a signal indicative of the detected fault.
    Type: Application
    Filed: November 5, 2021
    Publication date: May 11, 2023
    Inventors: Steven E. MULDOON, Yue-Yun Wang, Bin Li, Lei Hao
  • Publication number: 20230142690
    Abstract: A monitoring system for a battery system includes a battery system including a battery pack. The battery pack includes M battery modules, where M is an integer greater than zero. Each of the M battery modules includes C battery cells, where C is an integer greater than one. T temperature sensors configured to generate sensed temperatures of the M battery modules, where T is greater than or equal to M and less than M times C. A battery management module configured to perform battery impedance measurements on the C battery cells of the M battery modules; generate estimated temperatures for each of the C battery cells of the M battery modules based on the battery impedance measurements; and selectively detect at least one of the C battery cells having a cell outlier temperature based on the estimated temperatures of the C battery cells.
    Type: Application
    Filed: November 5, 2021
    Publication date: May 11, 2023
    Inventors: Steven E. MULDOON, Yue-Yun Wang, Lei Hao
  • Patent number: 11646346
    Abstract: A method of forming a semiconductor device structure is provided. The method includes forming an insulating layer over a semiconductor substrate including a conductive feature, forming an insulating layer with a trench over the semiconductor substrate to expose the conductive feature, and forming a sacrificial liner layer over two opposite sidewalls and a bottom of the trench. Ions are implanted into the conductive feature covered by the sacrificial liner layer, so that a doping region is formed in the conductive feature and has two opposite side edges respectively separated from the two opposite sidewalls of the trench. The sacrificial liner layer is removed after forming the doping region, and a conductive connecting structure is formed in the trench. The two opposite sidewalls of the conductive connecting structure are respectively separated from the two corresponding opposite sidewalls of the trench by an air spacer.
    Type: Grant
    Filed: April 8, 2021
    Date of Patent: May 9, 2023
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chung-Hao Cai, Chun-Po Chang, Chien-Yuan Chen, Yen-Jun Huang, Ting Fang, Chen-Ming Lee, Fu-Kai Yang, Mei-Yun Wang
  • Patent number: 11639534
    Abstract: A device for double-sided processing through single shot peening includes: a shot peening system, a workpiece clamping mechanism for clamping a workpiece, and a rebound system. The workpiece is provided with a first through-hole, and the first through-hole directly faces a nozzle. The rebound system includes a reflecting surface, an open container, and a reflecting surface gripping unit. The reflecting surface includes an upper reflecting surface, a middle reflecting surface, and a lower reflecting surface. The middle reflecting surface is provided with a second through-hole. The upper reflecting surface and the lower reflecting surface are both made of flexible elastic materials and are both provided with waterproof layers. A partition plate is disposed in the open container and partitions the open container into a first cavity and a second cavity. The second cavity is provided with a filling liquid, and the partition plate is slidable in the open container.
    Type: Grant
    Filed: July 23, 2020
    Date of Patent: May 2, 2023
    Assignee: JIANGSU UNIVERSITY
    Inventors: Fuzhu Li, Shangshuang Chen, Yun Wang, Jun Guo, Haiyang Fan, Yuqin Guo, Hong Liu, Cheng Zhang, Weichao Wan, Bin Zhang
  • Patent number: 11640936
    Abstract: A semiconductor structure and the manufacturing method thereof are disclosed. An exemplary semiconductor structure includes a first source/drain contact and a second source/drain contact spaced apart by a gate structure, an etch stop layer (ESL) over the first source/drain contact and the second source/drain contact, a conductive feature disposed in the etch stop layer and in direct contact with the first source/drain contact and the second source/drain contact, a dielectric layer over the etch stop layer, and a contact via extending through the dielectric layer and electrically connected to the conductive feature. By providing the conductive feature, a number of metal lines in an interconnect structure of the semiconductor structure may be advantageously reduced.
    Type: Grant
    Filed: January 8, 2021
    Date of Patent: May 2, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Chao-Hsun Wang, Wang-Jung Hsueh, Fu-Kai Yang, Mei-Yun Wang, Sheng-Hsiung Wang, Shih-Hsien Huang
  • Publication number: 20230121981
    Abstract: A method for forming a semiconductor device includes forming a metal gate stack having a gate dielectric layer and a gate electrode disposed over the gate dielectric layer. The gate electrode includes a first metal layer and a second metal layer. The method further includes performing a plasma treatment to a top surface of the metal gate stack and forming a conductive layer over the treated top surface of the metal gate stack. A top portion of the conductive layer is formed above a top surface of the gate dielectric layer, and a bottom portion of the conductive layer penetrates into the first and the second metal layers of the gate electrode at different distances.
    Type: Application
    Filed: December 16, 2022
    Publication date: April 20, 2023
    Inventors: Chao-Hsun Wang, Yu-Feng Yin, Kuo-Yi Chao, Mei-Yun Wang, Feng-Yu Chang, Chen-Yuan Kao
  • Patent number: 11626459
    Abstract: A displaying base plate includes an opening region, an adjacent region surrounding the opening region, and a displaying region surrounding the adjacent region, and the displaying base plate located within the adjacent region includes: a substrate base plate; a flat layer and a passivation layer that are provided on one side of the substrate base plate, wherein the passivation layer is provided on one side of the flat layer that is further away from the substrate base plate, a surface of the one side of the flat layer that is further away from the substrate base plate includes at least an inclined plane adjacent to one side of the opening region, and the flat layer includes a first protrusion provided on the inclined plane; and a first isolating groove that at least partially overlaps with the first protrusion and extends throughout the passivation layer and extends into the first protrusion.
    Type: Grant
    Filed: June 11, 2021
    Date of Patent: April 11, 2023
    Assignees: Chengdu BOE Optoelectronics Technology Co., Ltd., BOE Technology Group Co., Ltd.
    Inventors: Xing Xiong, Yun Wang, Li Liu, Qinglin Wen, Chunlei Xu, Minghui Wang