Abstract: A pixel array includes a plurality of dark pixel sensors configured to generate dark current calibration information for a plurality of visible light pixel sensors included in the pixel array. The plurality of dark pixel sensors may generate respective dark current measurements for each of the plurality of visible light pixel sensors or for small subsets of the plurality of visible light pixel sensors. In this way, each of the plurality of visible light pixel sensors may be individually calibrated (or small subsets of the plurality of visible light pixel sensors may be individually calibrated) based on an estimated dark current experienced by each of the plurality of visible light pixel sensors. This may enable more accurate dark current calibration of the visible light pixel sensors included in the pixel array, and may be used to account for large differences in estimated dark currents for the visible light pixel sensors.

Abstract: A system for the cryptographically-secure, autonomous control of devices comprising, connected to or remotely operating devices in an electrically powered network and the transaction of the benefits, costs or value created by or transacted through the devices in this electrically powered network.

Abstract: A semiconductor structure includes a first interposer; a second interposer laterally adjacent to the first interposer, where the second interposer is spaced apart from the first interposer; and a first die attached to a first side of the first interposer and attached to a first side of the second interposer, where the first side of the first interposer and the first side of the second interposer face the first die.

Abstract: Embodiments of the present disclosure relate to a solution for translation verification and correction. According to the solution, a neural network is trained to determine an association degree among a group of words in a source or target language. The neural network can be used for translation verification and correction. According to the solution, a group of words in a source language and translations of the group of words in a target language are obtained. An association degree among the group of words and an association degree among the translations can be determined by using the trained neural network. Then, whether there is a wrong translation can be determined based on the association degrees. In some embodiments, corresponding methods, systems and computer program products are provided.

Abstract: A battery pack, comprising a first cell and a second cell connected in series, the first cell having a current cut-off device and having a first failure voltage, the current cut-off device being configured to be able to break a circuit in response to a voltage value of the first cell reaching or exceeding the first failure voltage, and the second cell having no current cut-off device. The battery pack may use a soft pack battery as the second cell, having advantages such as high energy density, low impedance, high discharge power, a low rate of temperature rise during high-rate discharge, and flexibility in dimensions.

Abstract: Microelectromechanical devices and methods of manufacture are presented. Embodiments include bonding a mask substrate to a first microelectromechanical system (MEMS) device. After the bonding has been performed, the mask substrate is patterned. A first conductive pillar is formed within the mask substrate, and a second conductive pillar is formed within the mask substrate, the second conductive pillar having a different height from the first conductive pillar. The mask substrate is then removed.

Abstract: Semiconductor devices and methods of manufacturing the semiconductor devices are presented. In embodiments the methods of manufacturing include depositing a first bonding layer on a first substrate, wherein the first substrate comprises a semiconductor substrate and a metallization layer. The first bonding layer and the semiconductor substrate are patterned to form first openings. A second substrate is bonded to the first substrate. After the bonding the second substrate, the second substrate is patterned to form second openings, at least one of the second openings exposing at least one of the first openings. After the patterning the second substrate, a third substrate is bonded to the second substrate, and after the bonding the third substrate, the third substrate is patterned to form third openings, at least one of the third openings exposing at least one of the second openings.

Abstract: A method includes forming a dummy gate over a semiconductor fin; forming a source/drain epitaxial structure over the semiconductor fin and adjacent to the dummy gate; depositing an interlayer dielectric (ILD) layer to cover the source/drain epitaxial structure; replacing the dummy gate with a gate structure; forming a dielectric structure to cut the gate structure, wherein a portion of the dielectric structure is embedded in the ILD layer; recessing the portion of the dielectric structure embedded in the ILD layer; after recessing the portion of the dielectric structure, removing a portion of the ILD layer over the source/drain epitaxial structure; and forming a source/drain contact in the ILD layer and in contact with the portion of the dielectric structure.

Abstract: The present application provides a method for analyzing droplets on the basis of volume distribution including obtaining a total volume V of a sample containing target molecules based on a system prepared using the sample. The system is emulsified into droplets. A droplet system is obtained when the droplets obtaining the sample executes an amplification reaction. A droplet image of the droplet system is obtained. A total number n of droplets included in the droplet system is obtained based on the droplet image. A droplet volume distribution of the droplet system is obtained based on the droplet image. A number j of negative droplets among the n droplets is counted. A quantitative analysis is performed for the target molecules according to the total volume V of the sample, the total number n of droplets, the droplet volume distribution information, and the number j of negative droplets.

Abstract: A semiconductor chip and a manufacturing method thereof are provided. The semiconductor chip includes: an array of pillar structures, disposed on a front surface of the semiconductor chip, and respectively including a ground pillar and multiple working pillars laterally spaced apart from and substantially parallel with a line portion of the ground pillar; and dummy pillar structures, disposed on the front surface of the semiconductor chip and laterally surrounding the pillar structures. Active devices formed inside the semiconductor chip are electrically connected to the working pillar. The ground pillars of the pillar structures and the dummy pillar structures are electrically connected to form a current pathway on the front surface of the semiconductor chip.

Abstract: According to an aspect, a computer-implemented method includes accessing a profile of a user that indicates a likelihood that the user will execute each of a plurality of types of processing when training a new AI model. A runtime matrix that includes identifiers of runtime environments is accessed. The matrix also includes, for each of the runtime environments, a frequency of use of the runtime environment to train previously trained AI models using each of the plurality of types of processing. One or more of the runtime environments is selected for output to the user based at least in part on the profile of the user and the runtime matrix. Identifiers of the selected one or more of the runtime environments are output to a user interface of the user along with a suggestion to use one of the selected one or more of the runtime environments.

Abstract: An image sensor device has a first number of first pixels disposed in a substrate and a second number of second pixels disposed in the substrate. The first number is substantially equal to the second number. A light-blocking structure disposed over the first pixels and the second pixels. The light-blocking structure defines a plurality of first openings and second openings through which light can pass. The first openings are disposed over the first pixels. The second openings are disposed over the second pixels. The second openings are smaller than the first openings. A microcontroller is configured to turn on different ones of the second pixels at different points in time.

Abstract: A metal mask has a first surface, a second surface opposite to the first surface, first and second openings provided on the first and second surfaces respectively, and first and second through holes communicating with the first and second openings respectively. The juncture of the first and second through holes further has an annular protrusion. The mask satisfies the in equations: 1 ? ?m 2 < 1 2 × W × H < 15 ? ?m 2 ? and ? 30 ? ° < ? < 65 ? ° , wherein W is the horizontal distance between an edge of the first opening and an imaginary connecting line passing through an edge of the second opening and an end edge of the annular protrusion, H is the vertical distance between the end edge of the annular protrusion and the first surface, and ? is the included angle between the imaginary connecting line and an imaginary extending plane of the first surface. The metal mask is effective in reducing shadow effect, thereby improving evaporation quality.

Abstract: The present disclosure provides a semiconductor structure and a method of manufacturing the same. The semiconductor structure includes a sensing device, a solar cell, and an interconnecting structure. The solar cell is disposed above the sensing device and is electrically connected to the sensing device. The interconnecting structure is disposed between the sensing device and the solar cell and has a first surface facing the solar cell and a second surface facing the sensing devices. The interconnecting structure comprises a first energy storage component and a second energy storage component. The first energy storage component is disposed closer to the first surface of the interconnecting structure than the second energy storage component.

Abstract: A semiconductor structure includes a substrate with a first surface and a second surface opposite to the first surface, a first and a second shallow trench isolations disposed in the substrate and on the second surface, a deep trench isolation structure in the substrate and coupled to the first shallow trench isolation, a first dielectric layer disposed on the first surface and coupled to the deep trench isolation structure, a second dielectric layer disposed over the first dielectric layer and coupled to the deep trench isolation structure, a third dielectric layer comprising a horizontal portion disposed over the second dielectric layer and a vertical portion coupled to the horizontal portion, and a through substrate via structure penetrating the substrate from the first surface to the second surface and penetrating the second shallow trench isolation.

Abstract: The image sensing structure includes a first semiconductor device and a second semiconductor device. The first semiconductor device includes at least one first unit. The at least one first unit includes a plurality of first interconnects adjacent to the top side of the first semiconductor device, a row selector, and an analog-to-digital converter (ADC) connected to the row selectors. The second semiconductor device includes at least one second unit. The at least one second unit includes a photodiode facing the top side of the second semiconductor device. The photodiode is configured to receive the light incident on the top side of the second semiconductor device. The top side of the first semiconductor device is bonded to the bottom side of the second semiconductor device.

Abstract: Embodiments of the invention are directed to computer-implemented methods of analyzing a web-based software application. A non-limiting example of the computer implemented method includes generating, using a processor system, a set of to-be-tested element-event pairs of the web-based software application. A set of compatibility tests is received at the processor system, where the set of compatibility tests is operable to perform compatibility testing of a corresponding set of element-event pairs. A comparison is performed between the set of to-be-tested element-event pairs and the corresponding set of element-event pairs. A compatibility testing recommendation is generated based at least in part on a result of the comparison.

Abstract: A semiconductor structure includes a semiconductor substrate, first to third isolation structures, and a conductive feature. The first to third isolation structures are over the semiconductor substrate and spaced apart from each other. The semiconductor substrate comprises a region surrounded by a sidewall of the first isolation structure and a first sidewall of the second isolation structure. The conductive feature extends vertically in the semiconductor substrate and between the between the second and third isolation structures, wherein the conductive feature has a rounded corner adjoining a second sidewall of the second isolation structure opposite the first sidewall of the second isolation structure.

Abstract: A pharmaceutical composition containing a mixed polymeric micelle and a drug enclosed in the micelle, in which the mixed polymeric micelle, 1 to 1000 nm in size, includes an amphiphilic block copolymer and a lipopolymer. Also disclosed are preparation of the pharmaceutical composition and use thereof for treating cancer.

Abstract: Embodiments of this application relate to the video coding and compression field, and disclose an encoding method and apparatus, and a decoding method and apparatus, to resolve a problem that an existing split mode cannot satisfy a relatively complex texture requirement. The decoding method specifically includes: parsing a bitstream to determine a basic split mode for a current to-be-decoded picture block and a target derivation mode for a subpicture block of the current to-be-decoded picture block; splitting the current to-be-decoded picture block into N subpicture blocks in the basic split mode, where N is an integer greater than or equal to 2; deriving one derived picture block from at least two adjacent subpicture blocks in the N subpicture blocks in the target derivation mode; and decoding the derived picture block.