Patents by Inventor Yun Wei

Yun Wei has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20230111199
    Abstract: An automatic floor-disinfection robot for floors of hospital rooms, including a moving device, a alarm and a disinfection device. The moving device is a disc-shaped robot, and includes a chassis moving mechanism, a support plate and a top plate arranged successively from bottom to top. The disinfection device includes a disinfection assembly and a baffle. The disinfection assembly includes a liquid supply mechanism, a liquid spray mechanism and a fan.
    Type: Application
    Filed: December 8, 2022
    Publication date: April 13, 2023
    Inventors: Xianghui CHANG, Bowen MA, Qijun LIU, Xia LIU, Yan YAN, Weidong QIU, Xihao JIN, Xiang LI, Miao ZHANG, Yun WEI
  • Patent number: 11626435
    Abstract: An image sensor includes a substrate, a photosensitive unit in the substrate, a dielectric grid over the substrate, and a color filter over the photosensitive unit and surrounded by the dielectric grid. The dielectric grid has a first portion and a second portion over the first portion, and the second portion of the dielectric grid has a rounded top surface extending upwards from a sidewall of the first portion of the dielectric grid. The color filter has a first portion lower than a lowermost portion of the rounded top surface of the second portion of the dielectric grid and a second portion higher than the lowermost portion of the rounded top surface of the second portion of the dielectric grid.
    Type: Grant
    Filed: September 11, 2020
    Date of Patent: April 11, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Yun-Wei Cheng, Chun-Hao Chou, Yin-Chieh Huang, Wan-Chen Huang, Zhe-Ju Liu, Kuo-Cheng Lee, Chi-Cherng Jeng
  • Patent number: 11621231
    Abstract: Leadless power amplifier (PA) packages and methods for fabricating leadless PA packages having topside terminations are disclosed. In embodiments, the method includes providing electrically-conductive pillar supports and a base flange. At least a first radio frequency (RF) power die is attached to a die mount surface of the base flange and electrically interconnected with the pillar supports. Pillar contacts are further provided, with the pillar contacts electrically coupled to the pillar supports and projecting therefrom in a package height direction. The first RF power die is enclosed in a package body, which at least partially defines a package topside surface opposite a lower surface of the base flange. Topside input/out terminals are formed, which are accessible from the package topside surface and which are electrically interconnected with the first RF power die through the pillar contacts and the pillar supports.
    Type: Grant
    Filed: April 15, 2022
    Date of Patent: April 4, 2023
    Assignee: NXP USA, Inc.
    Inventors: Yun Wei, Fernando A. Santos, Lakshminarayan Viswanathan, Scott Duncan Marshall
  • Patent number: 11610638
    Abstract: A sample holding circuit includes a signal input terminal, a first sampling unit, a second sampling unit, and a holding unit. The signal input terminal receives a first reference voltage or a second reference voltage, the first sampling unit samples the first reference voltage when a first clock signal is triggered to obtain a first sampling voltage, the second sampling unit samples the second reference voltage when a second clock signal is triggered to obtain a second sampling voltage. The holding unit receives the first sampling voltage and the second sampling voltage when a third clock signal is triggered. The sample holding circuit effectively simplifies circuit structure and reduces the use of amplifiers, also improving the signal to noise ratio.
    Type: Grant
    Filed: August 3, 2021
    Date of Patent: March 21, 2023
    Assignee: JADARD TECHNOLOGY INC.
    Inventors: Feng-Wei Lin, Yu-Chieh Hsu, Hong-Yun Wei
  • Publication number: 20230078927
    Abstract: A method of manufacturing a transistor structure includes forming a plurality of trenches in a substrate, lining the plurality of trenches with a dielectric material, forming first and second substrate regions at opposite sides of the plurality of trenches, and filling the plurality of trenches with a conductive material. The plurality of trenches includes first and second trenches aligned between the first and second substrate regions, and filling the plurality of trenches with the conductive material includes the conductive material extending continuously between the first and second trenches.
    Type: Application
    Filed: November 11, 2022
    Publication date: March 16, 2023
    Inventors: Kun-Huei LIN, Yun-Wei CHENG, Chun-Hao CHOU, Kuo-Cheng LEE, Chun-Wei CHIA
  • Publication number: 20230067395
    Abstract: In some implementations, a pixel array may include a near infrared (NIR) cut filter layer for visible light pixel sensors of the pixel array. The NIR cut filter layer is included in the pixel array to absorb or reflect NIR light for the visible light pixel sensors to reduce the amount of MR light absorbed by the visible light pixel sensors. This increases the accuracy of the color information provided by the visible light pixel sensors, which can be used to produce more accurate images. In some implementations, the visible light pixel sensors and/or MR pixel sensors may include high absorption regions to adjust the orientation of the angle of refraction for the visible light pixel sensors and/or the MR pixel sensors, which may increase the quantum efficiency of the visible light pixel sensors and/or the MR pixel sensors.
    Type: Application
    Filed: August 30, 2021
    Publication date: March 2, 2023
    Inventors: Feng-Chien HSIEH, Yun-Wei CHENG, Kuo-Cheng LEE, Cheng-Ming WU
  • Publication number: 20230068723
    Abstract: A semiconductor arrangement includes a photodiode extending to a first depth from a first side in a substrate. An isolation structure laterally surrounds the photodiode and includes a first well that extends into a first side of the substrate. A deep trench isolation extends into a second side of the substrate and at least a portion of the deep trench isolation underlies the first well.
    Type: Application
    Filed: August 27, 2021
    Publication date: March 2, 2023
    Inventors: Feng-Chien HSIEH, Yun-Wei CHENG, Kuo-Cheng LEE, Cheng-Ming WU
  • Patent number: 11586948
    Abstract: An IoT system includes a computing module for controlling an integral function of the system and including an analysis unit and a machine learning unit. The analysis unit is capable of operational analysis and creating a predictive model and creating a predictive model according to the data analyzed. The machine learning unit has an algorithm function to create a corresponding learning model. An IoT module is electrically connected to the computing module to serve as an intermediate role. At least one detection unit is electrically connected to the IoT module and disposed in soil to detect data of environmental and soil conditions and sends the data detected to the computing module for subsequent analysis.
    Type: Grant
    Filed: October 20, 2019
    Date of Patent: February 21, 2023
    Assignee: National Yang Ming Chiao Tung University
    Inventors: Wen-Liang Chen, Lung-Chieh Chen, Szu-Chia Chen, Wei-Han Chen, Chun-Yu Chu, Yu-Chi Shih, Yu-Ci Chang, Tzu-I Hsieh, Yen-Ling Chen, Li-Chi Peng, Meng-Zhan Lee, Jui-Yu Ho, Chi-Yao Ku, Nian-Ruei Deng, Yuan-Yao Chan, Erick Wang, Tai-Hsiang Yen, Shao-Yu Chiu, Jiun-Yi Lin, Yun-Wei Lin, Fung Ling Ng, Yi-Bing Lin, Chin-Cheng Wang
  • Patent number: 11581352
    Abstract: Some aspects of the present disclosure relate to a method. In the method, a semiconductor substrate is received. A photodetector is formed in the semiconductor substrate. An interconnect structure is formed over the photodetector and over a frontside of the semiconductor substrate. A backside of the semiconductor substrate is thinned, the backside being furthest from the interconnect structure. A ring-shaped structure is formed so as to extend into the thinned backside of the semiconductor substrate to laterally surround the photodetector. A series of trench structures are formed to extend into the thinned backside of the semiconductor substrate. The series of trench structures are laterally surrounded by the ring-shaped structure and extend into the photodetector.
    Type: Grant
    Filed: January 25, 2021
    Date of Patent: February 14, 2023
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yun-Wei Cheng, Chun-Hao Chou, Kuo-Cheng Lee
  • Patent number: 11569289
    Abstract: A semiconductor structure includes a substrate having a pixel array region and a first seal ring region, wherein the first seal ring region surrounds the pixel array region, and the first seal ring region includes a first seal ring. The semiconductor structure further includes a first isolation feature in the first seal ring region, wherein the first isolation feature is filled with a dielectric material, and the first isolation feature is a continuous structure surrounding the pixel array region. The semiconductor structure further includes a second isolation feature between the first isolation feature and the pixel array region, wherein the second isolation feature is filled with the dielectric material.
    Type: Grant
    Filed: August 24, 2021
    Date of Patent: January 31, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Yun-Wei Cheng, Chun-Wei Chia, Chun-Hao Chou, Kuo-Cheng Lee, Ying-Hao Chen
  • Patent number: 11569288
    Abstract: A semiconductor structure includes a sensor chip. The sensor chip includes a pixel array region, a bonding pad region, and a periphery region surrounding the pixel array region. The semiconductor structure further includes a stress-releasing trench, wherein the stress-releasing trench is in the periphery region, and the stress-releasing trench fully surrounds a perimeter of the pixel array region and the bonding pad region.
    Type: Grant
    Filed: April 8, 2021
    Date of Patent: January 31, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Yun-Wei Cheng, Chun-Wei Chia, Chun-Hao Chou, Kuo-Cheng Lee, Ying-Hao Chen
  • Publication number: 20220406391
    Abstract: A sample holding circuit includes a signal input terminal, a first sampling unit, a second sampling unit, and a holding unit. The signal input terminal receives a first reference voltage or a second reference voltage, the first sampling unit samples the first reference voltage when a first clock signal is triggered to obtain a first sampling voltage, the second sampling unit samples the second reference voltage when a second clock signal is triggered to obtain a second sampling voltage. The holding unit receives the first sampling voltage and the second sampling voltage when a third clock signal is triggered. The sample holding circuit effectively simplifies circuit structure and reduces the use of amplifiers, also improving the signal to noise ratio.
    Type: Application
    Filed: August 3, 2021
    Publication date: December 22, 2022
    Inventors: FENG-WEI LIN, YU-CHIEH HSU, HONG-YUN WEI
  • Patent number: 11527563
    Abstract: A semiconductor structure includes a photodetector, which includes a substrate semiconductor layer having a doping of a first conductivity type, a second-conductivity-type photodiode layer that forms a p-n junction with the substrate semiconductor layer, a floating diffusion region that is laterally spaced from the second-conductivity-type photodiode layer, and a transfer gate electrode including a lower transfer gate electrode portion that is formed within the substrate semiconductor layer and located between the second-conductivity-type photodiode layer and the floating diffusion region. The transfer gate electrode may laterally surround the p-n junction, and may provide enhanced electron transmission efficiency from the p-n junction to the floating diffusion region. An array of photodetectors may be used to provide an image sensor.
    Type: Grant
    Filed: April 20, 2020
    Date of Patent: December 13, 2022
    Inventors: Feng-Chien Hsieh, Yun-Wei Cheng, Wei-Li Hu, Kuo-Cheng Lee, Hsin-Chi Chen
  • Patent number: 11521997
    Abstract: An IC structure includes a substrate region having a first doping type and including an upper surface, first and second regions within the substrate region, each of the first and second regions having a second doping type opposite the first doping type, and a gate conductor including a plurality of conductive protrusions extending into the substrate region in a direction perpendicular to a plane of the upper surface. The conductive protrusions are electrically connected to each other, and at least a portion of each conductive protrusion is positioned between the first and second regions.
    Type: Grant
    Filed: April 16, 2020
    Date of Patent: December 6, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Kun-Huei Lin, Yun-Wei Cheng, Chun-Hao Chou, Kuo-Cheng Lee, Chun-Wei Chia
  • Publication number: 20220384497
    Abstract: An image sensor with stress adjusting layers and a method of fabrication the image sensor are disclosed. The image sensor includes a substrate with a front side surface and a back side surface opposite to the front side surface, an anti-reflective coating (ARC) layer disposed on the back side surface of the substrate, a dielectric layer disposed on the ARC layer, a metal layer disposed on the dielectric layer, and a stress adjusting layer disposed on the metal layer. The stress adjusting layer includes a silicon-rich oxide layer. The concentration profiles of silicon and oxygen atoms in the stress adjusting layer are non-overlapping and different from each other. The image sensor further includes oxide grid structure disposed on the stress adjusting layer.
    Type: Application
    Filed: July 29, 2022
    Publication date: December 1, 2022
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Feng-Chien HSIEH, Kuo-Cheng Lee, Ying-Hao Chen, Yun-Wei Cheng
  • Publication number: 20220384509
    Abstract: A method includes forming image sensors in a semiconductor substrate, thinning the semiconductor substrate from a backside of the semiconductor substrate, forming a dielectric layer on the backside of the semiconductor substrate, and forming a polymer grid on the backside of the semiconductor substrate. The polymer grid has a first refractivity value. The method further includes forming color filters in the polymer grid, wherein the color filters has a second refractivity value higher than the first refractivity value, and forming micro-lenses on the color filters.
    Type: Application
    Filed: August 9, 2022
    Publication date: December 1, 2022
    Inventors: Kun-Huei Lin, Yun-Wei Cheng, Chun-Hao Chou, Kuo-Cheng Lee, Cheng Yuan Wang
  • Publication number: 20220369521
    Abstract: In one aspect, a computing device-implemented method includes receiving at least one triggering event signal from one or more components of a heat recovery system. The method also includes determining, based in part on the at least one triggering event signal, a computation workload assignment to be executed on one or more computation devices. The method further includes sending one or more command signals to the one or more computation devices. The one or more command signals include a portion of the computation workload assignment for execution by the one or more computation devices. The method also includes initiating capture of heat energy to be stored in one or more heat reservoirs, the heat energy being generated by the one or more computation device based upon the computation workload assignment.
    Type: Application
    Filed: May 26, 2022
    Publication date: November 17, 2022
    Inventors: Lawrence Orsini, Yun Wei
  • Publication number: 20220367549
    Abstract: An image sensor device includes a substrate, photosensitive pixels, an interconnect structure, a dielectric layer, and a light blocking element. The photosensitive pixels are in the substrate. The interconnect structure is over a first side of the substrate. The dielectric layer is over a second side of the substrate opposite the first side of the substrate. The light blocking element has a first portion extending over a top surface of the dielectric layer and a second portion extending in the dielectric layer. The second portion of the light blocking element laterally surrounds the photosensitive pixels.
    Type: Application
    Filed: July 29, 2022
    Publication date: November 17, 2022
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Feng-Chien HSIEH, Yun-Wei CHENG, Wei-Li HU, Kuo-Cheng LEE, Ying-Hao CHEN
  • Publication number: 20220367546
    Abstract: A semiconductor structure includes a photodetector, which includes a substrate semiconductor layer having a doping of a first conductivity type, a second-conductivity-type photodiode layer that forms a p-n junction with the substrate semiconductor layer, a floating diffusion region that is laterally spaced from the second-conductivity-type photodiode layer, and a transfer gate electrode including a lower transfer gate electrode portion that is formed within the substrate semiconductor layer and located between the second-conductivity-type photodiode layer and the floating diffusion region. The transfer gate electrode may laterally surround the p-n junction, and may provide enhanced electron transmission efficiency from the p-n junction to the floating diffusion region. An array of photodetectors may be used to provide an image sensor.
    Type: Application
    Filed: July 19, 2022
    Publication date: November 17, 2022
    Inventors: Feng-Chien Hsieh, Yun-Wei Cheng, Wei-Li Hu, Kuo-Cheng Lee, Hsin-Chi Chen
  • Publication number: 20220363758
    Abstract: The present disclosure provides heterodimeric antibodies that bind to two different target antigens at the same time. In one embodiment, the heterodimeric antibodies are bispecific antibodies. In one embodiment, the heterodimeric antibodies comprise three polypeptides including: a first polypeptide comprising an scFv-Fc fusion polypeptide; a second polypeptide comprising an immunoglobulin heavy chain; and a third polypeptide comprising an immunoglobulin light chain. In one embodiment, the first polypeptide includes one or more point mutations that confer increased thermal-stability to the first polypeptide.
    Type: Application
    Filed: June 30, 2020
    Publication date: November 17, 2022
    Applicant: Sorrento Therapeutics, Inc.
    Inventors: Xiao He, Yanliang Zhang, Yun Wei Lai, Gunnar F. Kaufmann, Barbara A. Swanson, Lisa Diane Kerwin, Susan M. Richards