Patents by Inventor Yun Wei

Yun Wei has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11791299
    Abstract: Exemplary embodiments for redistribution layers of integrated circuits are disclosed. The redistribution layers of integrated circuits of the present disclosure include one or more arrays of conductive contacts that are configured and arranged to allow a bonding wave to displace air between the redistribution layers during bonding. This configuration and arrangement of the one or more arrays minimize discontinuities, such as pockets of air to provide an example, between the redistribution layers during the bonding.
    Type: Grant
    Filed: April 27, 2018
    Date of Patent: October 17, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Cheng-Yuan Li, Kuo-Cheng Lee, Yun-Wei Cheng, Yen-Liang Lin
  • Patent number: 11791358
    Abstract: A method of forming a semiconductor device includes forming photodiodes extending from a front-side surface of a semiconductor layer into the semiconductor layer; forming transistors on the front-side surface of the semiconductor layer; forming an interconnect structure over the transistors, the interconnect structure comprising an inter-metal dielectric and metal lines in the inter-metal dielectric; etching first regions of a backside surface of the semiconductor layer to form trenches in the semiconductor layer and non-overlapping the photodiodes; after forming the trenches, etching second regions of the backside surface of the semiconductor layer to form pits in the semiconductor layer and overlapping the photodiodes; and depositing a dielectric material in the trenches and the pits.
    Type: Grant
    Filed: August 7, 2021
    Date of Patent: October 17, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Yun-Wei Cheng, Chun-Hao Chou, Kuo-Cheng Lee
  • Publication number: 20230308755
    Abstract: An image sensor including a semiconductor substrate, a plurality of color filters, a plurality of first lenses and a second lens is provided. The semiconductor substrate includes a plurality of sensing pixels arranged in array, and each of the plurality of sensing pixels respectively includes a plurality of image sensing units and a plurality of phase detection units. The color filters at least cover the plurality of image sensing units. The first lenses are disposed on the plurality of color filters. Each of the plurality of first lenses respectively covers one of the plurality of image sensing units. The second lens is disposed on the plurality of color filters and the second lens covers the plurality of phase detection units.
    Type: Application
    Filed: June 1, 2023
    Publication date: September 28, 2023
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yun-Wei Cheng, Chun-Hao Chou, Hsin-Chi Chen, Kuo-Cheng Lee, Hsun-Ying Huang
  • Patent number: 11769780
    Abstract: An image sensor with stress adjusting layers and a method of fabrication the image sensor are disclosed. The image sensor includes a substrate with a front side surface and a back side surface opposite to the front side surface, an anti-reflective coating (ARC) layer disposed on the back side surface of the substrate, a dielectric layer disposed on the ARC layer, a metal layer disposed on the dielectric layer, and a stress adjusting layer disposed on the metal layer. The stress adjusting layer includes a silicon-rich oxide layer. The concentration profiles of silicon and oxygen atoms in the stress adjusting layer are non-overlapping and different from each other. The image sensor further includes oxide grid structure disposed on the stress adjusting layer.
    Type: Grant
    Filed: July 23, 2020
    Date of Patent: September 26, 2023
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Feng-Chien Hsieh, Kuo-Cheng Lee, Ying-Hao Chen, Yun-Wei Cheng
  • Publication number: 20230268367
    Abstract: An isolation structure can be formed between adjacent and/or non-adjacent pixel regions (e.g., between diagonal or cross-road pixel regions), of an image sensor, to reduce and/or prevent optical crosstalk. The isolation structure may include a deep trench isolation (DTI) structure or another type of trench that is partially filled with a material such that an air gap is formed therein. The DTI structure having the air gap formed therein may reduce optical crosstalk between pixel regions. The reduced optical crosstalk may increase spatial resolution of the image sensor, may increase overall sensitivity of the image sensor, may decrease color mixing between pixel regions of the image sensor, and/or may decrease image noise after color correction of images captured using the image sensor.
    Type: Application
    Filed: April 28, 2023
    Publication date: August 24, 2023
    Inventors: Tsung-Wei HUANG, Chao-Ching CHANG, Yun-Wei CHENG, Chih-Lung CHENG, Yen-Chang CHEN, Wen-Jen TSAI, Cheng Han LIN, Yu-Hsun CHIH, Sheng-Chan LI, Sheng-Chau CHEN
  • Patent number: 11736831
    Abstract: An image sensor includes a photosensitive sensor, a floating diffusion node, a reset transistor, and a source follower transistor. The reset transistor comprises a first source/drain coupled to the floating diffusion node and a second source/drain coupled to a first voltage source. The source follower transistor comprises a gate coupled to the floating diffusion node and a first source/drain coupled to the second source/drain of the reset transistor. A first elongated contact contacts the second source/drain of the reset transistor and the first source/drain of the source follower transistor. The first elongated contact has a first dimension in a horizontal cross-section and a second dimension in the horizontal cross-section. The second dimension is perpendicular to the first dimension, and the second dimension is less than the first dimension.
    Type: Grant
    Filed: November 8, 2021
    Date of Patent: August 22, 2023
    Assignee: Taiwan Semiconductor Manufacturing Company Limited
    Inventors: Yun-Wei Cheng, Chia Chun-Wei, Chun-Hao Chou, Kuo-Cheng Lee
  • Patent number: 11735618
    Abstract: A back side illumination (BSI) image sensor with a dielectric grid opening having a planar lower surface is provided. A pixel sensor is arranged within a semiconductor substrate. A metallic grid is arranged over the pixel sensor and defines a sidewall of a metallic grid opening. A dielectric grid is arranged over the metallic grid and defines a sidewall of the dielectric grid opening. A capping layer is arranged over the metallic grid, and defines the planar lower surface of the dielectric grid opening.
    Type: Grant
    Filed: August 13, 2021
    Date of Patent: August 22, 2023
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yun-Wei Cheng, Horng-Huei Tseng, Chao-Hsiung Wang, Chun-Hao Chou, Tsung-Han Tsai, Kuo-Cheng Lee, Tzu-Hsuan Hsu, Yung-Lung Hsu
  • Patent number: 11735619
    Abstract: Disclosed is a method of fabricating a semiconductor image sensor device. The method includes providing a substrate having a pixel region, a periphery region, and a bonding pad region. The substrate further has a first side and a second side opposite the first side. The pixel region contains radiation-sensing regions. The method further includes forming a bonding pad in the bonding pad region; and forming light-blocking structures over the second side of the substrate, at least in the pixel region, after the bonding pad has been formed.
    Type: Grant
    Filed: June 6, 2022
    Date of Patent: August 22, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD
    Inventors: Chiu-Jung Chen, Chun-Hao Chou, Hsin-Chi Chen, Kuo-Cheng Lee, Volume Chien, Yun-Wei Cheng
  • Patent number: 11728365
    Abstract: A semiconductor device includes a semiconductor substrate, a radiation-sensing region, at least one isolation structure, and a doped passivation layer. The radiation-sensing region is present in the semiconductor substrate. The isolation structure is present in the semiconductor substrate and adjacent to the radiation-sensing region. The doped passivation layer at least partially surrounds the isolation structure in a substantially conformal manner.
    Type: Grant
    Filed: January 27, 2021
    Date of Patent: August 15, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Tsung-Han Tsai, Yun-Wei Cheng, Kuo-Cheng Lee, Chun-Hao Chou, Yung-Lung Hsu
  • Patent number: 11728364
    Abstract: A method includes forming image sensors in a semiconductor substrate, thinning the semiconductor substrate from a backside of the semiconductor substrate, forming a dielectric layer on the backside of the semiconductor substrate, and forming a polymer grid on the backside of the semiconductor substrate. The polymer grid has a first refractivity value. The method further includes forming color filters in the polymer grid, wherein the color filters has a second refractivity value higher than the first refractivity value, and forming micro-lenses on the color filters.
    Type: Grant
    Filed: August 11, 2020
    Date of Patent: August 15, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Kun-Huei Lin, Yun-Wei Cheng, Chun-Hao Chou, Kuo-Cheng Lee, Cheng Yuan Wang
  • Publication number: 20230253284
    Abstract: The present disclosure describes heat dissipation structures formed in functional or non- functional areas of a three-dimensional chip structure. These heat dissipation structures are configured to route the heat generated within the three-dimensional chip structure to designated areas on or outside the three-dimensional chip structure. For example, the three-dimensional chip structure can include a plurality of chips vertically stacked on a substrate, a first passivation layer interposed between a first chip and a second chip of the plurality of chips, and a heat dissipation layer embedded in the first passivation layer and configured to allow conductive structures to pass through.
    Type: Application
    Filed: April 19, 2023
    Publication date: August 10, 2023
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Yun-Wei CHENG, Chun-Hao Chou, Kuo-Cheng Lee, Ying-Hao Chen
  • Publication number: 20230246047
    Abstract: An image sensor includes a substrate, a first photosensitive unit, a second photosensitive unit, a buffer layer, a dielectric grid, a first color filter, and a second color filter. The first photosensitive unit and the second photosensitive unit are in the substrate. The buffer layer covers the substrate, the first photosensitive unit and the second photosensitive unit. The dielectric grid is over the buffer layer and between the first photosensitive unit and the second photosensitive unit. The dielectric grid has a round top surface. The first color filter is over the first photosensitive unit. The first color filter is in contact with the round top surface and the buffer layer. The second color filter is over the second photosensitive unit.
    Type: Application
    Filed: April 10, 2023
    Publication date: August 3, 2023
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Yun-Wei CHENG, Chun-Hao CHOU, Yin-Chieh HUANG, Wan-Chen HUANG, Zhe-Ju LIU, Kuo-Cheng LEE, Chi-Cherng JENG
  • Patent number: 11706525
    Abstract: An image sensor including a semiconductor substrate, a plurality of color filters, a plurality of first lenses and a second lens is provided. The semiconductor substrate includes a plurality of sensing pixels arranged in array, and each of the plurality of sensing pixels respectively includes a plurality of image sensing units and a plurality of phase detection units. The color filters at least cover the plurality of image sensing units. The first lenses are disposed on the plurality of color filters. Each of the plurality of first lenses respectively covers one of the plurality of image sensing units. The second lens is disposed on the plurality of color filters and the second lens covers the plurality of phase detection units.
    Type: Grant
    Filed: October 4, 2021
    Date of Patent: July 18, 2023
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yun-Wei Cheng, Chun-Hao Chou, Hsin-Chi Chen, Kuo-Cheng Lee, Hsun-Ying Huang
  • Publication number: 20230214387
    Abstract: Computer technology for: (i) performing prefetching based on shard workload in NoSQL; and/or (ii) perform distribution of stored data over the various tiers of a cache memory based on shard workload in NoSQL. This can help achieve better load balance among and between the shards of a database and the respectively associated nodes on which the shards are stored.
    Type: Application
    Filed: January 5, 2022
    Publication date: July 6, 2023
    Inventors: Peng Hui Jiang, Gang Tang, Jun Su, Yan Chen, Yun Wei Qi
  • Patent number: 11684687
    Abstract: An automatic floor-disinfection robot for floors of hospital rooms, including a moving device, a alarm and a disinfection device. The moving device is a disc-shaped robot, and includes a chassis moving mechanism, a support plate and a top plate arranged successively from bottom to top. The disinfection device includes a disinfection assembly and a baffle. The disinfection assembly includes a liquid supply mechanism, a liquid spray mechanism and a fan.
    Type: Grant
    Filed: December 8, 2022
    Date of Patent: June 27, 2023
    Assignees: SOUTHWEST JIAOTONG UNIVERSITY, LAOKEN MEDICAL TECHNOLOGY CO., LTD.
    Inventors: Xianghui Chang, Bowen Ma, Qijun Liu, Xia Liu, Yan Yan, Weidong Qiu, Xihao Jin, Xiang Li, Miao Zhang, Yun Wei
  • Publication number: 20230197751
    Abstract: Some aspects of the present disclosure relate to a method. In the method, a semiconductor substrate is received. A photodetector is formed in the semiconductor substrate. An interconnect structure is formed over the photodetector and over a frontside of the semiconductor substrate. A backside of the semiconductor substrate is thinned, the backside being furthest from the interconnect structure. A ring-shaped structure is formed so as to extend into the thinned backside of the semiconductor substrate to laterally surround the photodetector. A series of trench structures are formed to extend into the thinned backside of the semiconductor substrate. The series of trench structures are laterally surrounded by the ring-shaped structure and extend into the photodetector.
    Type: Application
    Filed: February 9, 2023
    Publication date: June 22, 2023
    Inventors: Yun-Wei Cheng, Chun-Hao Chou, Kuo-Cheng Lee
  • Patent number: 11670651
    Abstract: A pixel array includes octagon-shaped pixel sensors and a combination of visible light pixel sensors (e.g., red, green, and blue pixel sensors) and near infrared (NIR) pixel sensors. The color information obtained by the visible light pixel sensors and the luminance obtained by the NIR pixel sensors may be combined to increase the low-light performance of the pixel array, and to allow for low-light color images in low-light applications. The octagon-shaped pixel sensors may be interspersed in the pixel array with square-shaped pixel sensors to increase the utilization of space in the pixel array, and to allow for pixel sensors in the pixel array to be sized differently. The capability to accommodate different sizes of visible light pixel sensors and NIR pixel sensors permits the pixel array to be formed and/or configured to satisfy various performance parameters.
    Type: Grant
    Filed: November 13, 2020
    Date of Patent: June 6, 2023
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Feng-Chien Hsieh, Yun-Wei Cheng, Kuo-Cheng Lee, Cheng-Ming Wu
  • Patent number: 11670562
    Abstract: The present disclosure describes heat dissipation structures formed in functional or non-functional areas of a three-dimensional chip structure. These heat dissipation structures are configured to route the heat generated within the three-dimensional chip structure to designated areas on or outside the three-dimensional chip structure. For example, the three-dimensional chip structure can include a plurality of chips vertically stacked on a substrate, a first passivation layer interposed between a first chip and a second chip of the plurality of chips, and a heat dissipation layer embedded in the first passivation layer and configured to allow conductive structures to pass through.
    Type: Grant
    Filed: November 30, 2020
    Date of Patent: June 6, 2023
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Yun-Wei Cheng, Chun-Hao Chou, Kuo-Cheng Lee, Ying-Hao Chen
  • Patent number: 11652124
    Abstract: An isolation structure can be formed between adjacent and/or non-adjacent pixel regions (e.g., between diagonal or cross-road pixel regions), of an image sensor, to reduce and/or prevent optical crosstalk. The isolation structure may include a deep trench isolation (DTI) structure or another type of trench that is partially filled with a material such that an air gap is formed therein. The DTI structure having the air gap formed therein may reduce optical crosstalk between pixel regions. The reduced optical crosstalk may increase spatial resolution of the image sensor, may increase overall sensitivity of the image sensor, may decrease color mixing between pixel regions of the image sensor, and/or may decrease image noise after color correction of images captured using the image sensor.
    Type: Grant
    Filed: October 14, 2020
    Date of Patent: May 16, 2023
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Tsung-Wei Huang, Chao-Ching Chang, Yun-Wei Cheng, Chih-Lung Cheng, Yen-Chang Chen, Wen-Jen Tsai, Cheng Han Lin, Yu-Hsun Chih, Sheng-Chan Li, Sheng-Chau Chen
  • Publication number: 20230115340
    Abstract: Leadless power amplifier (PA) packages having topside termination interposer (TTI) arrangements, and associated fabrication methods, are disclosed. Embodiments of the leadless PA package include a base flange, a first set of interposer mount pads, a first RF power die, a package body. The first RF power die is attached to a die mount surface of the base flange and electrically interconnected with the first set of interposer mount pads. The TTI arrangement is electrically coupled to the first set of interposer mount pads and projects therefrom in the package height direction. The package body encloses the first RF power die and having a package topside surface opposite the lower flange surface. Topside input/output terminals of the PA package are accessible from the package topside surface and are electrically interconnected with the first RF power die through the TTI arrangement and the first set of interposer mount pads.
    Type: Application
    Filed: September 30, 2021
    Publication date: April 13, 2023
    Inventors: Yun Wei, Scott Duncan Marshall, Lakshminarayan Viswanathan, Taek Kyu Kim, Ricardo Uscola, Fernando A. Santos